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Searched refs:BankBaseAddr (Results 1 – 25 of 33) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/gpd/hal/k6lite/gpd/
H A Dgpd_reg.c1034 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr) in hal_gpd_init_outside_reg() argument
1038 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x42*2*2)); in hal_gpd_init_outside_reg()
1041 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x42*2*2)) = tmp; in hal_gpd_init_outside_reg()
1051 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x71200*2 + 0x10*2*2)) &= ~0x0020; in hal_gpd_init_outside_reg()
1059 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x15*2*2)); in hal_gpd_init_outside_reg()
1061 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x15*2*2)) = tmp; in hal_gpd_init_outside_reg()
1062 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x0d*2*2)) = 0x2b34; in hal_gpd_init_outside_reg()
1063 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x0d*2*2)) = 0x2b35; in hal_gpd_init_outside_reg()
1070 void hal_gpd_power_on(MS_VIRT BankBaseAddr) in hal_gpd_power_on() argument
1082 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0; // 0x28 << 2 in hal_gpd_power_on()
[all …]
H A Dgpd_reg.h313 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr);
314 void hal_gpd_power_on(MS_VIRT BankBaseAddr);
315 void hal_gpd_power_off(MS_VIRT BankBaseAddr);
317 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable);
/utopia/UTPA2-700.0.x/modules/gpd/hal/k6/gpd/
H A Dgpd_reg.c1034 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr) in hal_gpd_init_outside_reg() argument
1038 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x42*2*2)); in hal_gpd_init_outside_reg()
1041 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x42*2*2)) = tmp; in hal_gpd_init_outside_reg()
1051 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x71200*2 + 0x10*2*2)) &= ~0x0020; in hal_gpd_init_outside_reg()
1059 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x15*2*2)); in hal_gpd_init_outside_reg()
1061 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x15*2*2)) = tmp; in hal_gpd_init_outside_reg()
1062 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x0d*2*2)) = 0x2b34; in hal_gpd_init_outside_reg()
1063 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x0d*2*2)) = 0x2b35; in hal_gpd_init_outside_reg()
1070 void hal_gpd_power_on(MS_VIRT BankBaseAddr) in hal_gpd_power_on() argument
1082 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0; // 0x28 << 2 in hal_gpd_power_on()
[all …]
H A Dgpd_reg.h313 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr);
314 void hal_gpd_power_on(MS_VIRT BankBaseAddr);
315 void hal_gpd_power_off(MS_VIRT BankBaseAddr);
317 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable);
/utopia/UTPA2-700.0.x/modules/gpd/hal/curry/gpd/
H A Dgpd_reg.c1034 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr) in hal_gpd_init_outside_reg() argument
1038 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x42*2*2)); in hal_gpd_init_outside_reg()
1041 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x42*2*2)) = tmp; in hal_gpd_init_outside_reg()
1051 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x71200*2 + 0x10*2*2)) &= ~0x0008; in hal_gpd_init_outside_reg()
1078 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x71200*2 + 0x0a*2*2)) = 0x0052; in hal_gpd_init_outside_reg()
1088 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x15*2*2)); in hal_gpd_init_outside_reg()
1090 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x15*2*2)) = tmp; in hal_gpd_init_outside_reg()
1091 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x0d*2*2)) = 0x2b34; in hal_gpd_init_outside_reg()
1092 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x0d*2*2)) = 0x2b35; in hal_gpd_init_outside_reg()
1099 void hal_gpd_power_on(MS_VIRT BankBaseAddr) in hal_gpd_power_on() argument
[all …]
H A Dgpd_reg.h313 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr);
314 void hal_gpd_power_on(MS_VIRT BankBaseAddr);
315 void hal_gpd_power_off(MS_VIRT BankBaseAddr);
317 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable);
/utopia/UTPA2-700.0.x/modules/gpd/hal/kano/gpd/
H A Dgpd_reg.c1028 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr) in hal_gpd_init_outside_reg() argument
1032 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x42*2*2)); in hal_gpd_init_outside_reg()
1035 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x42*2*2)) = tmp; in hal_gpd_init_outside_reg()
1045 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x71200*2 + 0x0a*2*2)) = 0x00f0; in hal_gpd_init_outside_reg()
1068 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x71200*2 + 0x10*2*2)) &= ~0x0008; in hal_gpd_init_outside_reg()
1074 void hal_gpd_power_on(MS_VIRT BankBaseAddr) in hal_gpd_power_on() argument
1086 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0; // 0x28 << 2 in hal_gpd_power_on()
1089 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0x4; in hal_gpd_power_on()
1092 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0xc; in hal_gpd_power_on()
1098 void hal_gpd_power_off(MS_VIRT BankBaseAddr) in hal_gpd_power_off() argument
[all …]
H A Dgpd_reg.h313 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr);
314 void hal_gpd_power_on(MS_VIRT BankBaseAddr);
315 void hal_gpd_power_off(MS_VIRT BankBaseAddr);
317 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable);
/utopia/UTPA2-700.0.x/modules/gpd/hal/manhattan/gpd/
H A Dgpd_reg.c1020 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr) in hal_gpd_init_outside_reg() argument
1024 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)); in hal_gpd_init_outside_reg()
1027 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)) = tmp; in hal_gpd_init_outside_reg()
1031 void hal_gpd_power_on(MS_VIRT BankBaseAddr) in hal_gpd_power_on() argument
1043 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0; // 0x28 << 2 in hal_gpd_power_on()
1046 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0x4; in hal_gpd_power_on()
1049 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0xc; in hal_gpd_power_on()
1055 void hal_gpd_power_off(MS_VIRT BankBaseAddr) in hal_gpd_power_off() argument
1064 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x71200*2 + 0x10*2*2)) |= 0x0008; in hal_gpd_power_off()
1067 UNUSED(BankBaseAddr); in hal_gpd_power_off()
[all …]
H A Dgpd_reg.h313 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr);
314 void hal_gpd_power_on(MS_VIRT BankBaseAddr);
315 void hal_gpd_power_off(MS_VIRT BankBaseAddr);
317 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable);
/utopia/UTPA2-700.0.x/modules/gpd/hal/maxim/gpd/
H A Dgpd_reg.c1029 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr) in hal_gpd_init_outside_reg() argument
1033 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)); in hal_gpd_init_outside_reg()
1036 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)) = tmp; in hal_gpd_init_outside_reg()
1047 void hal_gpd_power_on(MS_VIRT BankBaseAddr) in hal_gpd_power_on() argument
1059 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0; // 0x28 << 2 in hal_gpd_power_on()
1062 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0x4; in hal_gpd_power_on()
1065 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0xc; in hal_gpd_power_on()
1071 void hal_gpd_power_off(MS_VIRT BankBaseAddr) in hal_gpd_power_off() argument
1084 UNUSED(BankBaseAddr); in hal_gpd_power_off()
1093 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable) in hal_gpd_SetMIUProtectMask() argument
[all …]
H A Dgpd_reg.h314 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr);
315 void hal_gpd_power_on(MS_VIRT BankBaseAddr);
316 void hal_gpd_power_off(MS_VIRT BankBaseAddr);
318 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable);
/utopia/UTPA2-700.0.x/modules/gpd/hal/M7621/gpd/
H A Dgpd_reg.c1029 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr) in hal_gpd_init_outside_reg() argument
1033 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)); in hal_gpd_init_outside_reg()
1036 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)) = tmp; in hal_gpd_init_outside_reg()
1047 void hal_gpd_power_on(MS_VIRT BankBaseAddr) in hal_gpd_power_on() argument
1059 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0; // 0x28 << 2 in hal_gpd_power_on()
1062 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0x4; in hal_gpd_power_on()
1065 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0xc; in hal_gpd_power_on()
1071 void hal_gpd_power_off(MS_VIRT BankBaseAddr) in hal_gpd_power_off() argument
1084 UNUSED(BankBaseAddr); in hal_gpd_power_off()
1093 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable) in hal_gpd_SetMIUProtectMask() argument
[all …]
H A Dgpd_reg.h314 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr);
315 void hal_gpd_power_on(MS_VIRT BankBaseAddr);
316 void hal_gpd_power_off(MS_VIRT BankBaseAddr);
318 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable);
/utopia/UTPA2-700.0.x/modules/gpd/hal/M7821/gpd/
H A Dgpd_reg.c1029 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr) in hal_gpd_init_outside_reg() argument
1033 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)); in hal_gpd_init_outside_reg()
1036 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)) = tmp; in hal_gpd_init_outside_reg()
1047 void hal_gpd_power_on(MS_VIRT BankBaseAddr) in hal_gpd_power_on() argument
1059 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0; // 0x28 << 2 in hal_gpd_power_on()
1062 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0x4; in hal_gpd_power_on()
1065 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0xc; in hal_gpd_power_on()
1071 void hal_gpd_power_off(MS_VIRT BankBaseAddr) in hal_gpd_power_off() argument
1084 UNUSED(BankBaseAddr); in hal_gpd_power_off()
1093 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable) in hal_gpd_SetMIUProtectMask() argument
[all …]
H A Dgpd_reg.h313 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr);
314 void hal_gpd_power_on(MS_VIRT BankBaseAddr);
315 void hal_gpd_power_off(MS_VIRT BankBaseAddr);
317 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable);
/utopia/UTPA2-700.0.x/modules/gpd/hal/maserati/gpd/
H A Dgpd_reg.c1029 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr) in hal_gpd_init_outside_reg() argument
1033 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)); in hal_gpd_init_outside_reg()
1036 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)) = tmp; in hal_gpd_init_outside_reg()
1047 void hal_gpd_power_on(MS_VIRT BankBaseAddr) in hal_gpd_power_on() argument
1059 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0; // 0x28 << 2 in hal_gpd_power_on()
1062 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0x4; in hal_gpd_power_on()
1065 *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0xc; in hal_gpd_power_on()
1071 void hal_gpd_power_off(MS_VIRT BankBaseAddr) in hal_gpd_power_off() argument
1084 UNUSED(BankBaseAddr); in hal_gpd_power_off()
1093 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable) in hal_gpd_SetMIUProtectMask() argument
[all …]
H A Dgpd_reg.h313 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr);
314 void hal_gpd_power_on(MS_VIRT BankBaseAddr);
315 void hal_gpd_power_off(MS_VIRT BankBaseAddr);
317 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable);
/utopia/UTPA2-700.0.x/modules/gpd/hal/maldives/gpd/
H A Dgpd_reg.c1007 void hal_gpd_init_outside_reg(U32 BankBaseAddr) in hal_gpd_init_outside_reg() argument
1010 tmp = *((volatile U32 *)(BankBaseAddr + 0x1E00*2 + 0x23*2*2)); in hal_gpd_init_outside_reg()
1013 *((volatile U32 *)(BankBaseAddr + 0x1E00*2 + 0x23*2*2)) = tmp; in hal_gpd_init_outside_reg()
1022 void hal_gpd_SetMIUProtectMask(U32 BankBaseAddr, U8 bEnable) in hal_gpd_SetMIUProtectMask() argument
1025 tmp = *((volatile U32 *)(BankBaseAddr + 0x1200*2 + 0x43*2*2)); in hal_gpd_SetMIUProtectMask()
1034 *((volatile U32 *)(BankBaseAddr + 0x1200*2 + 0x43*2*2)) = tmp; in hal_gpd_SetMIUProtectMask()
1036 tmp = *((volatile U32 *)(BankBaseAddr + 0x0600*2 + 0x43*2*2)); in hal_gpd_SetMIUProtectMask()
1045 *((volatile U32 *)(BankBaseAddr + 0x0600*2 + 0x43*2*2)) = tmp; in hal_gpd_SetMIUProtectMask()
/utopia/UTPA2-700.0.x/modules/gpd/hal/mustang/gpd/
H A Dgpd_reg.c1013 void hal_gpd_init_outside_reg(U32 BankBaseAddr) in hal_gpd_init_outside_reg() argument
1017 tmp = *((volatile U32 *)(BankBaseAddr + 0x1E00*2 + 0x21*2*2)); in hal_gpd_init_outside_reg()
1020 *((volatile U32 *)(BankBaseAddr + 0x1E00*2 + 0x21*2*2)) = tmp; in hal_gpd_init_outside_reg()
1029 void hal_gpd_SetMIUProtectMask(U32 BankBaseAddr, U8 bEnable) in hal_gpd_SetMIUProtectMask() argument
1034 tmp = *((volatile U32 *)(BankBaseAddr + 0x1200*2 + 0x33*2*2)); in hal_gpd_SetMIUProtectMask()
1043 *((volatile U32 *)(BankBaseAddr + 0x1200*2 + 0x33*2*2)) = tmp; in hal_gpd_SetMIUProtectMask()
1045 tmp = *((volatile U32 *)(BankBaseAddr + 0x0600*2 + 0x33*2*2)); in hal_gpd_SetMIUProtectMask()
1054 *((volatile U32 *)(BankBaseAddr + 0x0600*2 + 0x33*2*2)) = tmp; in hal_gpd_SetMIUProtectMask()
/utopia/UTPA2-700.0.x/modules/gpd/hal/mainz/gpd/
H A Dgpd_reg.c1014 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr) in hal_gpd_init_outside_reg() argument
1018 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)); in hal_gpd_init_outside_reg()
1021 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)) = tmp; in hal_gpd_init_outside_reg()
1030 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable) in hal_gpd_SetMIUProtectMask() argument
1034 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x43*2*2)); in hal_gpd_SetMIUProtectMask()
1043 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x43*2*2)) = tmp; in hal_gpd_SetMIUProtectMask()
1045 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x0600*2 + 0x43*2*2)); in hal_gpd_SetMIUProtectMask()
1054 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x0600*2 + 0x43*2*2)) = tmp; in hal_gpd_SetMIUProtectMask()
/utopia/UTPA2-700.0.x/modules/gpd/hal/messi/gpd/
H A Dgpd_reg.c1014 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr) in hal_gpd_init_outside_reg() argument
1018 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)); in hal_gpd_init_outside_reg()
1021 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)) = tmp; in hal_gpd_init_outside_reg()
1030 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable) in hal_gpd_SetMIUProtectMask() argument
1034 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x43*2*2)); in hal_gpd_SetMIUProtectMask()
1043 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x43*2*2)) = tmp; in hal_gpd_SetMIUProtectMask()
1045 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x0600*2 + 0x43*2*2)); in hal_gpd_SetMIUProtectMask()
1054 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x0600*2 + 0x43*2*2)) = tmp; in hal_gpd_SetMIUProtectMask()
/utopia/UTPA2-700.0.x/modules/gpd/hal/mooney/gpd/
H A Dgpd_reg.c1015 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr) in hal_gpd_init_outside_reg() argument
1019 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)); in hal_gpd_init_outside_reg()
1022 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)) = tmp; in hal_gpd_init_outside_reg()
1031 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable) in hal_gpd_SetMIUProtectMask() argument
1035 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x43*2*2)); in hal_gpd_SetMIUProtectMask()
1044 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x43*2*2)) = tmp; in hal_gpd_SetMIUProtectMask()
1046 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x0600*2 + 0x43*2*2)); in hal_gpd_SetMIUProtectMask()
1055 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x0600*2 + 0x43*2*2)) = tmp; in hal_gpd_SetMIUProtectMask()
/utopia/UTPA2-700.0.x/modules/gpd/hal/macan/gpd/
H A Dgpd_reg.c1015 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr) in hal_gpd_init_outside_reg() argument
1020 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)); in hal_gpd_init_outside_reg()
1023 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x22*2*2)) = tmp; in hal_gpd_init_outside_reg()
1032 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable) in hal_gpd_SetMIUProtectMask() argument
1036 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x43*2*2)); in hal_gpd_SetMIUProtectMask()
1045 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x43*2*2)) = tmp; in hal_gpd_SetMIUProtectMask()
1047 tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x0600*2 + 0x43*2*2)); in hal_gpd_SetMIUProtectMask()
1056 *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x0600*2 + 0x43*2*2)) = tmp; in hal_gpd_SetMIUProtectMask()
/utopia/UTPA2-700.0.x/modules/gpd/api/gpd/
H A DapiGPD.c459 MS_VIRT BankBaseAddr; in _GPD_SetAccessRegion() local
465 if(FALSE == MDrv_MMIO_GetBASE((MS_VIRT*)&BankBaseAddr, &BankSize, MS_MODULE_GPD)) in _GPD_SetAccessRegion()
471 pGPDContext->GpdAddrInfo.RegBaseAddr = BankBaseAddr + (MS_VIRT)u32GPDRIUBase; in _GPD_SetAccessRegion()
558 MS_VIRT BankBaseAddr; in _MApi_GPD_Init() local
579 if(FALSE == MDrv_MMIO_GetBASE(&BankBaseAddr, &BankSize, MS_MODULE_GPD)) in _MApi_GPD_Init()
586 pGPDContext->RIU_REG_BASE = BankBaseAddr; in _MApi_GPD_Init()
587 …BaseAddr = %tx, BankSize = %tx\n", __FUNCTION__, __LINE__, (ptrdiff_t)BankBaseAddr, (ptrdiff_t)Ban… in _MApi_GPD_Init()
597 drv_gpd_init_outside_reg(BankBaseAddr); in _MApi_GPD_Init()
601 g_gpd_clock = (BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET); in _MApi_GPD_Init()
603 (ptrdiff_t)BankBaseAddr, (ptrdiff_t)GPD_CLK_BASE, (ptrdiff_t)GPD_CLK_OFFSET); in _MApi_GPD_Init()
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