1028 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr)  in hal_gpd_init_outside_reg()  argument
1032     tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x42*2*2));  in hal_gpd_init_outside_reg()
1035     *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1E00*2 + 0x42*2*2)) = tmp;  in hal_gpd_init_outside_reg()
1045     *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x71200*2 + 0x0a*2*2)) = 0x00f0;  in hal_gpd_init_outside_reg()
1068     *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x71200*2 + 0x10*2*2)) &= ~0x0008;  in hal_gpd_init_outside_reg()
1074 void hal_gpd_power_on(MS_VIRT BankBaseAddr)  in hal_gpd_power_on()  argument
1086         *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0;   // 0x28 << 2  in hal_gpd_power_on()
1089         *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0x4;  in hal_gpd_power_on()
1092         *((volatile MS_U32 *)(BankBaseAddr + GPD_CLK_BASE + GPD_CLK_OFFSET)) = 0xc;  in hal_gpd_power_on()
1098 void hal_gpd_power_off(MS_VIRT BankBaseAddr)  in hal_gpd_power_off()  argument
1107     *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x71200*2 + 0x10*2*2)) |= 0x0008;  in hal_gpd_power_off()
1110     UNUSED(BankBaseAddr);  in hal_gpd_power_off()
1119 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable)  in hal_gpd_SetMIUProtectMask()  argument
1123     tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x43*2*2));  in hal_gpd_SetMIUProtectMask()
1132     *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x1200*2 + 0x43*2*2)) = tmp;  in hal_gpd_SetMIUProtectMask()
1134     tmp = *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x0600*2 + 0x43*2*2));  in hal_gpd_SetMIUProtectMask()
1143     *((volatile MS_U32 *)(MS_VIRT)(BankBaseAddr + 0x0600*2 + 0x43*2*2)) = tmp;  in hal_gpd_SetMIUProtectMask()