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Searched refs:AEON_REG8 (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/uart/hal/k6lite/uart/
H A DhalUART.c566 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
567 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
583 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
587 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
639 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
640 buf[nr_recv++] = AEON_REG8(UART_RX); in HAL_UART_Aeon_Read()
683 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
700 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
743 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
744 AEON_REG8(UART_DLL) = divisor & 0xFF; in HAL_UART_Aeon_Set_Baudrate()
[all …]
H A DhalUART.h120 #define AEON_REG8(_x_) ((MS_U8 volatile *)(UART_BASE))[(_x_)] macro
/utopia/UTPA2-700.0.x/modules/uart/hal/curry/uart/
H A DhalUART.c566 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
567 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
583 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
587 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
639 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
640 buf[nr_recv++] = AEON_REG8(UART_RX); in HAL_UART_Aeon_Read()
683 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
700 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
743 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
744 AEON_REG8(UART_DLL) = divisor & 0xFF; in HAL_UART_Aeon_Set_Baudrate()
[all …]
H A DhalUART.h120 #define AEON_REG8(_x_) ((MS_U8 volatile *)(UART_BASE))[(_x_)] macro
/utopia/UTPA2-700.0.x/modules/uart/hal/kano/uart/
H A DhalUART.c566 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
567 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
583 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
587 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
639 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
640 buf[nr_recv++] = AEON_REG8(UART_RX); in HAL_UART_Aeon_Read()
683 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
700 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
743 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
744 AEON_REG8(UART_DLL) = divisor & 0xFF; in HAL_UART_Aeon_Set_Baudrate()
[all …]
H A DhalUART.h120 #define AEON_REG8(_x_) ((MS_U8 volatile *)(UART_BASE))[(_x_)] macro
/utopia/UTPA2-700.0.x/modules/uart/hal/k6/uart/
H A DhalUART.c566 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
567 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
583 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
587 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
639 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
640 buf[nr_recv++] = AEON_REG8(UART_RX); in HAL_UART_Aeon_Read()
683 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
700 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
743 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
744 AEON_REG8(UART_DLL) = divisor & 0xFF; in HAL_UART_Aeon_Set_Baudrate()
[all …]
H A DhalUART.h120 #define AEON_REG8(_x_) ((MS_U8 volatile *)(UART_BASE))[(_x_)] macro
/utopia/UTPA2-700.0.x/modules/uart/hal/mooney/uart/
H A DhalUART.c587 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
588 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
604 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
608 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
660 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
661 buf[nr_recv++] = AEON_REG8(UART_RX); in HAL_UART_Aeon_Read()
704 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
721 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
764 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
765 AEON_REG8(UART_DLL) = divisor & 0xFF; in HAL_UART_Aeon_Set_Baudrate()
[all …]
H A DhalUART.h120 #define AEON_REG8(_x_) ((MS_U8 volatile *)(UART_BASE))[(_x_)] macro
/utopia/UTPA2-700.0.x/modules/uart/hal/mustang/uart/
H A DhalUART.c582 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
583 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
599 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
603 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
655 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
656 buf[nr_recv++] = AEON_REG8(UART_RX); in HAL_UART_Aeon_Read()
699 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
716 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
760 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
761 AEON_REG8(UART_DLL) = divisor & 0xFF; in HAL_UART_Aeon_Set_Baudrate()
[all …]
H A DhalUART.h120 #define AEON_REG8(_x_) ((MS_U8 volatile *)(UART_BASE))[(_x_)] macro
/utopia/UTPA2-700.0.x/modules/uart/hal/maldives/uart/
H A DhalUART.c582 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
583 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
599 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
603 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
655 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
656 buf[nr_recv++] = AEON_REG8(UART_RX); in HAL_UART_Aeon_Read()
699 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
716 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
760 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
761 AEON_REG8(UART_DLL) = divisor & 0xFF; in HAL_UART_Aeon_Set_Baudrate()
[all …]
H A DhalUART.h120 #define AEON_REG8(_x_) ((MS_U8 volatile *)(UART_BASE))[(_x_)] macro
/utopia/UTPA2-700.0.x/modules/uart/hal/macan/uart/
H A DhalUART.c612 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
613 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
629 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
633 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
685 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
686 buf[nr_recv++] = AEON_REG8(UART_RX); in HAL_UART_Aeon_Read()
729 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
746 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
789 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
790 AEON_REG8(UART_DLL) = divisor & 0xFF; in HAL_UART_Aeon_Set_Baudrate()
[all …]
H A DhalUART.h120 #define AEON_REG8(_x_) ((MS_U8 volatile *)(UART_BASE))[(_x_)] macro
/utopia/UTPA2-700.0.x/modules/uart/hal/messi/uart/
H A DhalUART.c611 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
612 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
628 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
632 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
684 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
685 buf[nr_recv++] = AEON_REG8(UART_RX); in HAL_UART_Aeon_Read()
728 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
745 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
788 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
789 AEON_REG8(UART_DLL) = divisor & 0xFF; in HAL_UART_Aeon_Set_Baudrate()
[all …]
H A DhalUART.h120 #define AEON_REG8(_x_) ((MS_U8 volatile *)(UART_BASE))[(_x_)] macro
/utopia/UTPA2-700.0.x/modules/uart/hal/M7621/uart/
H A DhalUART.c615 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
616 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
632 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
636 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
688 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
689 buf[nr_recv++] = AEON_REG8(UART_RX); in HAL_UART_Aeon_Read()
732 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
749 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
792 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
793 AEON_REG8(UART_DLL) = divisor & 0xFF; in HAL_UART_Aeon_Set_Baudrate()
[all …]
/utopia/UTPA2-700.0.x/modules/uart/hal/maserati/uart/
H A DhalUART.c615 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
616 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
632 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
636 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
688 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
689 buf[nr_recv++] = AEON_REG8(UART_RX); in HAL_UART_Aeon_Read()
732 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
749 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
792 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
793 AEON_REG8(UART_DLL) = divisor & 0xFF; in HAL_UART_Aeon_Set_Baudrate()
[all …]
/utopia/UTPA2-700.0.x/modules/uart/hal/maxim/uart/
H A DhalUART.c615 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
616 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
632 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
636 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
688 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
689 buf[nr_recv++] = AEON_REG8(UART_RX); in HAL_UART_Aeon_Read()
732 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
749 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
792 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
793 AEON_REG8(UART_DLL) = divisor & 0xFF; in HAL_UART_Aeon_Set_Baudrate()
[all …]
/utopia/UTPA2-700.0.x/modules/uart/hal/manhattan/uart/
H A DhalUART.c614 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
615 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
631 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
635 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
687 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
688 buf[nr_recv++] = AEON_REG8(UART_RX); in HAL_UART_Aeon_Read()
731 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
748 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
791 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
792 AEON_REG8(UART_DLL) = divisor & 0xFF; in HAL_UART_Aeon_Set_Baudrate()
[all …]
/utopia/UTPA2-700.0.x/modules/uart/hal/M7821/uart/
H A DhalUART.c615 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
616 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
632 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
636 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
688 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
689 buf[nr_recv++] = AEON_REG8(UART_RX); in HAL_UART_Aeon_Read()
732 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
749 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
792 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
793 AEON_REG8(UART_DLL) = divisor & 0xFF; in HAL_UART_Aeon_Set_Baudrate()
[all …]
/utopia/UTPA2-700.0.x/modules/uart/hal/mainz/uart/
H A DhalUART.c657 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
658 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
674 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
678 AEON_REG8(UART_TX) = *buf++; in HAL_UART_Aeon_Write()
730 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
731 buf[nr_recv++] = AEON_REG8(UART_RX); in HAL_UART_Aeon_Read()
774 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
791 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
834 AEON_REG8(UART_LCR) |= UART_LCR_DLAB; in HAL_UART_Aeon_Set_Baudrate()
835 AEON_REG8(UART_DLL) = divisor & 0xFF; in HAL_UART_Aeon_Set_Baudrate()
[all …]
H A DhalUART.h120 #define AEON_REG8(_x_) ((MS_U8 volatile *)(UART_BASE))[(_x_)] macro

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