Searched refs:tile_width (Results 1 – 4 of 4) sorted by relevance
465 RK_S32 tile_width; in h265e_set_pps() local489 tile_width = (index + 1) * mb_w / (pps->m_nNumTileColumnsMinus1 + 1) - in h265e_set_pps()491 pps->m_nTileColumnWidthArray[index] = tile_width; in h265e_set_pps()494 tile_width = mb_w - index * mb_w / (pps->m_nNumTileColumnsMinus1 + 1); in h265e_set_pps()495 pps->m_nTileColumnWidthArray[index] = tile_width; in h265e_set_pps()
636 RK_S32 tile_width[64] = {0}; in prepare_uncompress_header() local650 tile_width[i] = (tile_col_end - tile_col_start + 7) / 8; in prepare_uncompress_header()663 mpp_put_bits(&bp, tile_width[i], 10); in prepare_uncompress_header()
1642 RK_S32 tile_width = syn->pp.column_width_minus1[index] + 1; in hal_h265e_v540_set_uniform_tile() local1644 regs->tile_cfg.tile_width_m1 = tile_width - 1; in hal_h265e_v540_set_uniform_tile()1646 regs->rc_cfg.rc_ctu_num = tile_width; in hal_h265e_v540_set_uniform_tile()
2815 RK_S32 tile_width = syn->pp.column_width_minus1[index] + 1; in hal_h265e_v580_set_uniform_tile() local2844 regs->reg0252_tile_cfg.tile_w_m1 = tile_width - 1; in hal_h265e_v580_set_uniform_tile()2846 regs->reg212_rc_cfg.rc_ctu_num = tile_width; in hal_h265e_v580_set_uniform_tile()