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Searched refs:sw_refer0_base (Results 1 – 6 of 6) sorted by relevance

/rockchip-linux_mpp/mpp/hal/vpu/mpg4d/
H A Dhal_m4vd_vdpu1.c143 regs->SwReg14.sw_refer0_base = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
147 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_ref1; in vdpu1_mpg4d_setup_regs_by_syntax()
150 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
178 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_ref0; in vdpu1_mpg4d_setup_regs_by_syntax()
181 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
196 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
H A Dhal_m4vd_vdpu1_reg.h168 RK_U32 sw_refer0_base : 32; member
/rockchip-linux_mpp/mpp/hal/vpu/h263d/
H A Dhal_h263d_vdpu1.c99 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_ref0; in vpu1_h263d_setup_regs_by_syntax()
102 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr; in vpu1_h263d_setup_regs_by_syntax()
109 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr; in vpu1_h263d_setup_regs_by_syntax()
H A Dhal_h263d_vdpu1_reg.h167 RK_U32 sw_refer0_base : 32; member
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu1_reg.h182 RK_U32 sw_refer0_base : 32; member
H A Dhal_h264d_vdpu1.c283 p_regs->SwReg14.sw_refer0_base = val; in vdpu1_set_refer_pic_base_addr()