Searched refs:src_udfo (Results 1 – 14 of 14) sorted by relevance
278 regs->src_udfo.csc_ofst_y = 16; in vepu511_set_jpeg_reg()279 regs->src_udfo.csc_ofst_u = 128; in vepu511_set_jpeg_reg()280 regs->src_udfo.csc_ofst_v = 128; in vepu511_set_jpeg_reg()
132 } src_udfo; member
504 regs->reg_base.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu540c_prep()505 regs->reg_base.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu540c_prep()506 regs->reg_base.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; in setup_vepu540c_prep()522 regs->reg_base.src_udfo.csc_ofst_y = cfg.offset[0]; in setup_vepu540c_prep()523 regs->reg_base.src_udfo.csc_ofst_u = cfg.offset[1]; in setup_vepu540c_prep()524 regs->reg_base.src_udfo.csc_ofst_v = cfg.offset[2]; in setup_vepu540c_prep()
785 regs->reg_base.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu580_prep()786 regs->reg_base.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu580_prep()787 regs->reg_base.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; in setup_vepu580_prep()803 regs->reg_base.src_udfo.csc_ofst_y = cfg.offset[0]; in setup_vepu580_prep()804 regs->reg_base.src_udfo.csc_ofst_u = cfg.offset[1]; in setup_vepu580_prep()805 regs->reg_base.src_udfo.csc_ofst_v = cfg.offset[2]; in setup_vepu580_prep()
801 reg_frm->common.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu510_prep()802 reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu510_prep()803 reg_frm->common.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; in setup_vepu510_prep()819 reg_frm->common.src_udfo.csc_ofst_y = cfg.offset[0]; in setup_vepu510_prep()820 reg_frm->common.src_udfo.csc_ofst_u = cfg.offset[1]; in setup_vepu510_prep()821 reg_frm->common.src_udfo.csc_ofst_v = cfg.offset[2]; in setup_vepu510_prep()
778 reg_frm->common.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu511_prep()779 reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu511_prep()780 reg_frm->common.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; in setup_vepu511_prep()796 reg_frm->common.src_udfo.csc_ofst_y = cfg.offset[0]; in setup_vepu511_prep()797 reg_frm->common.src_udfo.csc_ofst_u = cfg.offset[1]; in setup_vepu511_prep()798 reg_frm->common.src_udfo.csc_ofst_v = cfg.offset[2]; in setup_vepu511_prep()
436 } src_udfo; member
411 } src_udfo; member
226 } src_udfo; member
1119 regs->src_udfo.ofst_y = cfg_coeffs->_2y.offset; in vepu541_h265_set_pp_regs()1120 regs->src_udfo.ofst_u = cfg_coeffs->_2u.offset; in vepu541_h265_set_pp_regs()1121 regs->src_udfo.ofst_v = cfg_coeffs->_2v.offset; in vepu541_h265_set_pp_regs()
1487 reg_frm->common.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in vepu510_h265_set_pp_regs()1488 reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in vepu510_h265_set_pp_regs()1489 reg_frm->common.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; in vepu510_h265_set_pp_regs()
1210 reg_frm->common.src_udfo.csc_ofst_y = 0; in vepu511_h265_set_pp_regs()1211 reg_frm->common.src_udfo.csc_ofst_u = 128; in vepu511_h265_set_pp_regs()1212 reg_frm->common.src_udfo.csc_ofst_v = 128; in vepu511_h265_set_pp_regs()
597 } src_udfo; member
926 } src_udfo; member