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Searched refs:src_fmt (Results 1 – 25 of 28) sorted by relevance

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/rockchip-linux_mpp/mpp/hal/rkenc/jpege/
H A Dhal_jpege_vepu511.c227 regs->src_fmt.src_cfmt = fmt->format; in vepu511_set_jpeg_reg()
228 regs->src_fmt.alpha_swap = fmt->alpha_swap; in vepu511_set_jpeg_reg()
229 regs->src_fmt.rbuv_swap = fmt->rbuv_swap; in vepu511_set_jpeg_reg()
230 regs->src_fmt.src_range_trns_en = 0; in vepu511_set_jpeg_reg()
231 regs->src_fmt.src_range_trns_sel = 0; in vepu511_set_jpeg_reg()
232 regs->src_fmt.chroma_ds_mode = 0; in vepu511_set_jpeg_reg()
245 if (regs->src_fmt.src_cfmt == VEPU5xx_FMT_BGRA8888) in vepu511_set_jpeg_reg()
247 else if (regs->src_fmt.src_cfmt == VEPU5xx_FMT_BGR888 || in vepu511_set_jpeg_reg()
248 regs->src_fmt.src_cfmt == VEPU5xx_FMT_YUV444P || in vepu511_set_jpeg_reg()
249 regs->src_fmt.src_cfmt == VEPU5xx_FMT_YUV444SP) in vepu511_set_jpeg_reg()
[all …]
H A Dhal_jpege_vepu511_reg.h100 } src_fmt; member
H A Dhal_jpege_vpu720_reg.h266 RK_U32 src_fmt : 4; member
H A Dhal_jpege_vpu720.c473 reg_base->reg032_sw_src_fmt.src_fmt = ctx->fmt_cfg.input_format; in hal_jpege_vpu720_gen_regs()
/rockchip-linux_mpp/mpp/vproc/rga/test/
H A Drga_test.c23 MppFrameFormat src_fmt; member
106 cmd->src_fmt = (MppFrameFormat) atoi(next); in rga_test_parse_options()
107 err = ((cmd->src_fmt >= MPP_FMT_YUV_BUTT && cmd->src_fmt < MPP_FRAME_FMT_RGB) || in rga_test_parse_options()
108 cmd->src_fmt >= MPP_FMT_RGB_BUTT); in rga_test_parse_options()
163 cmd.src_w, cmd.src_h, cmd.src_fmt, in main()
224 cmd.src_w, cmd.src_h, cmd.src_fmt, frame_count); in main()
236 mpp_frame_set_fmt(src_frm, cmd.src_fmt); in main()
/rockchip-linux_mpp/mpp/vproc/iep2/test/
H A Diep2_test.c37 RK_S32 src_fmt; member
134 cfg->src_fmt, cfg->src_swa, in check_input_cmd()
137 if (cfg->src_fmt < IEP2_FMT_YUV422 || in check_input_cmd()
138 cfg->src_fmt > IEP2_FMT_YUV420 || in check_input_cmd()
199 size_t srcfrmsize = get_frm_size(cfg->src_fmt, cfg->w, cfg->h); in iep2_test()
284 params.param.com.sfmt = cfg->src_fmt; in iep2_test()
294 imgsrc[i].format = cfg->src_fmt; in iep2_test()
380 cfg.src_fmt = IEP2_FMT_YUV420; in main()
396 cfg.src_fmt = str_to_iep2_fmt(optarg); in main()
/rockchip-linux_mpp/mpp/vproc/iep/test/
H A Diep_test.c34 RK_S32 src_fmt; member
253 config_iep_img(&info->src, cfg->src_w, cfg->src_h, cfg->src_fmt, info->phy_src0); in iep_process_thread()
279 config_iep_img(&src1, cfg->src_w, cfg->src_h, cfg->src_fmt, info->phy_src1); in iep_process_thread()
280 config_iep_img(&dst1, cfg->src_w, cfg->src_h, cfg->src_fmt, info->phy_dst1); in iep_process_thread()
354 if (cfg->src_fmt < IEP_FORMAT_ARGB_8888 || in check_input_cmd()
355 cfg->src_fmt > IEP_FORMAT_YCrCb_420_P) { in check_input_cmd()
440 cfg.src_fmt = IEP_FORMAT_YCbCr_420_SP; in main()
454 cfg.src_fmt = str_to_iep_fmt(optarg); in main()
508 info.src_size = get_image_size(cfg.src_w, cfg.src_h, cfg.src_fmt); in main()
/rockchip-linux_mpp/mpp/vproc/rga/
H A Drga.c287 RgaFormat src_fmt = rga_fmt_map(mpp_frame_get_fmt(src)); in rga_copy() local
292 if (src_fmt >= RGA_FMT_BUTT || dst_fmt >= RGA_FMT_BUTT) { in rga_copy()
294 src_fmt, dst_fmt); in rga_copy()
307 src_fd, src_w, src_h, src_fmt, in rga_copy()
312 request->src.format = (RK_U32)src_fmt; in rga_copy()
/rockchip-linux_mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu_v2.c328 prep->src_fmt = format; in h264e_vepu_prep_setup()
340 prep->src_fmt = fmt_cfg.format; in h264e_vepu_prep_setup()
342 prep->src_fmt = VEPU_FMT_BUTT; in h264e_vepu_prep_setup()
347 if (prep->src_fmt == VEPU_FMT_BUTT) { in h264e_vepu_prep_setup()
359 if (prep->src_fmt == VEPU_FMT_BUTT) { in h264e_vepu_prep_setup()
H A Dhal_h264e_vepu_v2.h41 RK_S32 src_fmt; member
H A Dhal_h264e_vepu1_v2.c394 | VEPU_REG_IN_IMG_CTRL_FMT(hw_prep->src_fmt) in hal_h264e_vepu1_gen_regs_v2()
H A Dhal_h264e_vepu2_v2.c478 | VEPU_REG_IN_IMG_CTRL_FMT(hw_prep->src_fmt) in hal_h264e_vepu2_gen_regs_v2()
/rockchip-linux_mpp/mpp/vproc/vdpp/
H A Dvdpp2.c291 if (MPP_FRAME_FMT_IS_YUV(src_params->src_fmt)) { in update_dci_ctl()
292 dci_format = vdpp_src_yuv_cfg[src_params->src_fmt - MPP_FRAME_FMT_YUV].format; in update_dci_ctl()
293 dci_alpha_swap = vdpp_src_yuv_cfg[src_params->src_fmt - MPP_FRAME_FMT_YUV].alpha_swap; in update_dci_ctl()
294 dci_rbuv_swap = vdpp_src_yuv_cfg[src_params->src_fmt - MPP_FRAME_FMT_YUV].rbuv_swap; in update_dci_ctl()
295 } else if (MPP_FRAME_FMT_IS_RGB(src_params->src_fmt)) { in update_dci_ctl()
296 dci_format = vdpp_src_rgb_cfg[src_params->src_fmt - MPP_FRAME_FMT_RGB].format; in update_dci_ctl()
297 dci_alpha_swap = vdpp_src_rgb_cfg[src_params->src_fmt - MPP_FRAME_FMT_RGB].alpha_swap; in update_dci_ctl()
298 dci_rbuv_swap = vdpp_src_rgb_cfg[src_params->src_fmt - MPP_FRAME_FMT_RGB].rbuv_swap; in update_dci_ctl()
300 mpp_err("warning: invalid input format %d", src_params->src_fmt); in update_dci_ctl()
308 VDPP2_DBG(VDPP2_DBG_TRACE, "input format %d dci_format %d", src_params->src_fmt, dci_format); in update_dci_ctl()
[all …]
H A Dvdpp2.h191 RK_U32 src_fmt; member
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu510.c1413 reg_frm->common.src_fmt.src_cfmt = fmt->format; in vepu510_h265_set_pp_regs()
1414 reg_frm->common.src_fmt.alpha_swap = fmt->alpha_swap; in vepu510_h265_set_pp_regs()
1415 reg_frm->common.src_fmt.rbuv_swap = fmt->rbuv_swap; in vepu510_h265_set_pp_regs()
1417 …reg_frm->common.src_fmt.out_fmt = ((prep_cfg->format & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400) ? 0 … in vepu510_h265_set_pp_regs()
1452 if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_BGRA8888) in vepu510_h265_set_pp_regs()
1454 else if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_BGR888) in vepu510_h265_set_pp_regs()
1456 else if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_BGR565 || in vepu510_h265_set_pp_regs()
1457 reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_YUYV422 || in vepu510_h265_set_pp_regs()
1458 reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_UYVY422) in vepu510_h265_set_pp_regs()
1462 stridec = (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_YUV420SP || in vepu510_h265_set_pp_regs()
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H A Dhal_h265e_vepu541.c1071 regs->src_fmt.src_cfmt = fmt->format; in vepu541_h265_set_pp_regs()
1072 regs->src_fmt.alpha_swap = fmt->alpha_swap; in vepu541_h265_set_pp_regs()
1073 regs->src_fmt.rbuv_swap = fmt->rbuv_swap; in vepu541_h265_set_pp_regs()
1074 regs->src_fmt.src_range = fmt->src_range; in vepu541_h265_set_pp_regs()
1088 if (regs->src_fmt.src_cfmt == VEPU5xx_FMT_BGRA8888) in vepu541_h265_set_pp_regs()
1090 else if (regs->src_fmt.src_cfmt == VEPU5xx_FMT_BGR888) in vepu541_h265_set_pp_regs()
1092 else if (regs->src_fmt.src_cfmt == VEPU5xx_FMT_BGR565 || in vepu541_h265_set_pp_regs()
1093 regs->src_fmt.src_cfmt == VEPU5xx_FMT_YUYV422 || in vepu541_h265_set_pp_regs()
1094 regs->src_fmt.src_cfmt == VEPU5xx_FMT_UYVY422) in vepu541_h265_set_pp_regs()
1098 stridec = (regs->src_fmt.src_cfmt == VEPU5xx_FMT_YUV422SP || in vepu541_h265_set_pp_regs()
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H A Dhal_h265e_vepu511.c708 reg_frm->common.src_fmt.src_cfmt = VEPU5xx_FMT_YUV420SP; in vepu511_h265e_use_pass1_patch()
709 reg_frm->common.src_fmt.alpha_swap = 0; in vepu511_h265e_use_pass1_patch()
710 reg_frm->common.src_fmt.rbuv_swap = 0; in vepu511_h265e_use_pass1_patch()
711 reg_frm->common.src_fmt.out_fmt = 1; in vepu511_h265e_use_pass1_patch()
1155 reg_frm->common.src_fmt.src_cfmt = fmt->format; in vepu511_h265_set_pp_regs()
1156 reg_frm->common.src_fmt.alpha_swap = fmt->alpha_swap; in vepu511_h265_set_pp_regs()
1157 reg_frm->common.src_fmt.rbuv_swap = fmt->rbuv_swap; in vepu511_h265_set_pp_regs()
1159 reg_frm->common.src_fmt.out_fmt = (prep_cfg->format == MPP_FMT_YUV400) ? 0 : 1; in vepu511_h265_set_pp_regs()
1173 if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_BGRA8888) in vepu511_h265_set_pp_regs()
1175 else if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_BGR888) in vepu511_h265_set_pp_regs()
[all …]
H A Dhal_h265e_vepu541_reg.h194 } src_fmt; member
/rockchip-linux_mpp/mpp/vproc/iep2/
H A Diep2.c99 ctx->params.src_fmt = IEP2_FMT_YUV420; in iep2_init()
166 ctx->params.src_fmt = IEP2_FMT_YUV420; in iep2_init()
302 ctx->params.src_fmt = param->com.sfmt; in iep2_set_param()
H A Diep2.h47 uint32_t src_fmt; member
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu580.c725 regs->reg_base.src_fmt.src_cfmt = hw_fmt; in setup_vepu580_prep()
726 regs->reg_base.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu580_prep()
727 regs->reg_base.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu580_prep()
728 regs->reg_base.src_fmt.out_fmt = (fmt == MPP_FMT_YUV400) ? 0 : 1; in setup_vepu580_prep()
731 regs->reg_base.src_fmt.src_range = 1; in setup_vepu580_prep()
733 regs->reg_base.src_fmt.src_range = (prep->range == MPP_FRAME_RANGE_JPEG) ? 1 : 0; in setup_vepu580_prep()
863 regs->reg_base.src_fmt.src_cfmt = VEPU5xx_FMT_YUV420SP; in vepu580_h264e_use_pass1_patch()
864 regs->reg_base.src_fmt.alpha_swap = 0; in vepu580_h264e_use_pass1_patch()
865 regs->reg_base.src_fmt.rbuv_swap = 0; in vepu580_h264e_use_pass1_patch()
866 regs->reg_base.src_fmt.out_fmt = 1; in vepu580_h264e_use_pass1_patch()
H A Dhal_h264e_vepu510.c722 reg_frm->common.src_fmt.src_cfmt = hw_fmt; in setup_vepu510_prep()
723 reg_frm->common.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu510_prep()
724 reg_frm->common.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu510_prep()
725 reg_frm->common.src_fmt.out_fmt = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400 ? 0 : 1); in setup_vepu510_prep()
884 reg_frm->common.src_fmt.src_cfmt = VEPU5xx_FMT_YUV420SP; in vepu510_h264e_use_pass1_patch()
885 reg_frm->common.src_fmt.alpha_swap = 0; in vepu510_h264e_use_pass1_patch()
886 reg_frm->common.src_fmt.rbuv_swap = 0; in vepu510_h264e_use_pass1_patch()
887 reg_frm->common.src_fmt.out_fmt = 1; in vepu510_h264e_use_pass1_patch()
888 reg_frm->common.src_fmt.src_rcne = 1; in vepu510_h264e_use_pass1_patch()
H A Dhal_h264e_vepu511.c721 reg_frm->common.src_fmt.src_cfmt = hw_fmt; in setup_vepu511_prep()
722 reg_frm->common.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu511_prep()
723 reg_frm->common.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu511_prep()
724 reg_frm->common.src_fmt.out_fmt = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400 ? 0 : 1); in setup_vepu511_prep()
857 reg_frm->common.src_fmt.src_cfmt = VEPU5xx_FMT_YUV420SP; in vepu511_h264e_use_pass1_patch()
858 reg_frm->common.src_fmt.alpha_swap = 0; in vepu511_h264e_use_pass1_patch()
859 reg_frm->common.src_fmt.rbuv_swap = 0; in vepu511_h264e_use_pass1_patch()
860 reg_frm->common.src_fmt.out_fmt = 1; in vepu511_h264e_use_pass1_patch()
H A Dhal_h264e_vepu540c.c476 regs->reg_base.src_fmt.src_cfmt = hw_fmt; in setup_vepu540c_prep()
477 regs->reg_base.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu540c_prep()
478 regs->reg_base.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu540c_prep()
479 regs->reg_base.src_fmt.out_fmt = (fmt == MPP_FMT_YUV400) ? 0 : 1; in setup_vepu540c_prep()
H A Dhal_h264e_vepu540c_reg.h404 } src_fmt; member

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