Searched refs:reg2_dec_ctrl (Results 1 – 4 of 4) sorted by relevance
169 reg->reg2_dec_ctrl.sw_dec_out_tiled_e = 0; in hal_vp8_init_hwcfg()170 reg->reg2_dec_ctrl.sw_dec_scmd_dis = 0; in hal_vp8_init_hwcfg()171 reg->reg2_dec_ctrl.sw_dec_adv_pre_dis = 0; in hal_vp8_init_hwcfg()172 reg->reg2_dec_ctrl.sw_dec_latency = 0; in hal_vp8_init_hwcfg()174 reg->reg2_dec_ctrl.sw_dec_in_endian = 1; in hal_vp8_init_hwcfg()175 reg->reg2_dec_ctrl.sw_dec_out_endian = 1; in hal_vp8_init_hwcfg()176 reg->reg2_dec_ctrl.sw_dec_inswap32_e = 1; in hal_vp8_init_hwcfg()177 reg->reg2_dec_ctrl.sw_dec_outswap32_e = 1; in hal_vp8_init_hwcfg()178 reg->reg2_dec_ctrl.sw_dec_strswap32_e = 1; in hal_vp8_init_hwcfg()179 reg->reg2_dec_ctrl.sw_dec_strendian_e = 1; in hal_vp8_init_hwcfg()[all …]
78 } reg2_dec_ctrl; member
614 reg->reg2_dec_ctrl.sw_dec_out_tiled_e = 0; in jpegd_regs_init()615 reg->reg2_dec_ctrl.sw_dec_scmd_dis = DEC_VDPU1_SCMD_DISABLE; in jpegd_regs_init()616 reg->reg2_dec_ctrl.sw_dec_latency = DEC_VDPU1_LATENCY_COMPENSATION; in jpegd_regs_init()618 reg->reg2_dec_ctrl.sw_dec_in_endian = DEC_VDPU1_BIG_ENDIAN; in jpegd_regs_init()619 reg->reg2_dec_ctrl.sw_dec_out_endian = DEC_VDPU1_LITTLE_ENDIAN; in jpegd_regs_init()620 reg->reg2_dec_ctrl.sw_dec_strendian_e = DEC_VDPU1_LITTLE_ENDIAN; in jpegd_regs_init()621 reg->reg2_dec_ctrl.sw_dec_outswap32_e = DEC_VDPU1_LITTLE_ENDIAN; in jpegd_regs_init()622 reg->reg2_dec_ctrl.sw_dec_inswap32_e = 1; in jpegd_regs_init()623 reg->reg2_dec_ctrl.sw_dec_strswap32_e = 1; in jpegd_regs_init()627 reg->reg2_dec_ctrl.sw_dec_axi_rn_id = 0xff; in jpegd_regs_init()[all …]
283 } reg2_dec_ctrl; member