Searched refs:pp_m_output_mode (Results 1 – 3 of 3) sorted by relevance
383 regs->ctrl_regs.reg9.pp_m_output_mode = 0; in set_registers()391 regs->ctrl_regs.reg9.pp_m_output_mode = 2; in set_registers()399 regs->ctrl_regs.reg9.pp_m_output_mode = 1; in set_registers()
90 RK_U32 pp_m_output_mode : 2; member
908 hw_regs->ctrl_regs.reg9.pp_m_output_mode = 0; in hal_h265d_vdpu384a_gen_regs()917 hw_regs->ctrl_regs.reg9.pp_m_output_mode = 2; in hal_h265d_vdpu384a_gen_regs()933 hw_regs->ctrl_regs.reg9.pp_m_output_mode = 1; in hal_h265d_vdpu384a_gen_regs()