Searched refs:offset_rps (Results 1 – 7 of 7) sorted by relevance
85 RK_U32 offset_rps[MAX_GEN_REG]; member
144 reg_ctx->offset_rps[i] = RPS_OFFSET(i); in hal_h265d_vdpu382_init()152 reg_ctx->rps_offset = reg_ctx->offset_rps[0]; in hal_h265d_vdpu382_init()681 reg_ctx->rps_offset = reg_ctx->offset_rps[i]; in hal_h265d_vdpu382_gen_regs()
146 reg_ctx->offset_rps[i] = RPS_OFFSET(i); in hal_h265d_vdpu34x_init()154 reg_ctx->rps_offset = reg_ctx->offset_rps[0]; in hal_h265d_vdpu34x_init()875 reg_ctx->rps_offset = reg_ctx->offset_rps[i]; in hal_h265d_vdpu34x_gen_regs()
156 reg_ctx->offset_rps[i] = RPS_OFFSET(i); in hal_h265d_vdpu383_init()166 reg_ctx->rps_offset = reg_ctx->offset_rps[0]; in hal_h265d_vdpu383_init()891 reg_ctx->rps_offset = reg_ctx->offset_rps[i]; in hal_h265d_vdpu383_gen_regs()
143 RK_U32 offset_rps[VDPU34X_FAST_REG_SET_CNT]; member731 reg_ctx->offset_rps[i] = VDPU34X_RPS_OFFSET(i); in vdpu34x_h264d_init()738 reg_ctx->rps_offset = reg_ctx->offset_rps[0]; in vdpu34x_h264d_init()945 ctx->rps_offset = ctx->offset_rps[i]; in vdpu34x_h264d_gen_regs()
90 RK_U32 offset_rps[VDPU383_FAST_REG_SET_CNT]; member653 reg_ctx->offset_rps[i] = VDPU383_RPS_OFFSET(i); in vdpu383_h264d_init()662 reg_ctx->rps_offset = reg_ctx->offset_rps[0]; in vdpu383_h264d_init()866 ctx->rps_offset = ctx->offset_rps[i]; in vdpu383_h264d_gen_regs()
147 RK_U32 offset_rps[VDPU382_FAST_REG_SET_CNT]; member752 reg_ctx->offset_rps[i] = VDPU382_RPS_OFFSET(i); in vdpu382_h264d_init()759 reg_ctx->rps_offset = reg_ctx->offset_rps[0]; in vdpu382_h264d_init()974 ctx->rps_offset = ctx->offset_rps[i]; in vdpu382_h264d_gen_regs()