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Searched refs:mb_h (Results 1 – 25 of 27) sorted by relevance

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/rockchip-linux_mpp/utils/
H A Dmpp_enc_roi_utils.c194 RK_S32 mb_h = MPP_ALIGN(h, 64) / 64; in vepu54x_h265_set_roi() local
198 for (j = 0; j < mb_h; j++) { in vepu54x_h265_set_roi()
227 RK_S32 mb_h = MPP_ALIGN(ctx->h, 16) / 16; in gen_vepu54x_roi() local
229 RK_S32 stride_v = MPP_ALIGN(mb_h, 4); in gen_vepu54x_roi()
290 mpp_assert(pos_y_init >= 0 && pos_y_init < mb_h); in gen_vepu54x_roi()
291 mpp_assert(pos_y_end >= 0 && pos_y_end <= mb_h); in gen_vepu54x_roi()
464 RK_S32 mb_h = MPP_ALIGN(ctx->h, 16) / 16; in gen_vepu580_roi_h264() local
466 RK_S32 stride_v = MPP_ALIGN(mb_h, 4); in gen_vepu580_roi_h264()
481 for (j = 0; j < mb_h; j++) { in gen_vepu580_roi_h264()
675 RK_S32 mb_h = MPP_ALIGN(impl->h, 16) / 16; in mpp_enc_roi_init() local
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H A Dmpi_enc_utils.c1209 RK_U32 mb_h = step_y; in mpi_enc_gen_osd_data() local
1222 RK_U32 region_size = MPP_ALIGN(mb_w * mb_h * 256, 16); in mpi_enc_gen_osd_data()
1228 region->num_mb_y = mb_h; in mpi_enc_gen_osd_data()
1230 region->enable = (mb_w && mb_h); in mpi_enc_gen_osd_data()
1258 mb_h = region->num_mb_y; in mpi_enc_gen_osd_data()
1261 memset(ptr + buf_offset, k, mb_w * mb_h * 256); in mpi_enc_gen_osd_data()
/rockchip-linux_mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu2_v2.c290 RK_U32 mb_h = ctx->sps->pic_height_in_mbs; in setup_intra_refresh() local
312 top = mpp_clip(top, 0, mb_h); in setup_intra_refresh()
313 bottom = mpp_clip(bottom, 0, mb_h); in setup_intra_refresh()
316 bottom = mb_h; in setup_intra_refresh()
351 RK_U32 mb_h = ctx->sps->pic_height_in_mbs; in hal_h264e_vepu2_gen_regs_v2() local
359 mb_h = ctx->sps->pic_width_in_mbs; in hal_h264e_vepu2_gen_regs_v2()
400 if (mb_w * mb_h > 3600) in hal_h264e_vepu2_gen_regs_v2()
413 RK_U32 scaler = MPP_MAX(1, 200 / (mb_w + mb_h)); in hal_h264e_vepu2_gen_regs_v2()
508 val = VEPU_REG_ROI1_TOP_MB(mb_h) in hal_h264e_vepu2_gen_regs_v2()
509 | VEPU_REG_ROI1_BOTTOM_MB(mb_h) in hal_h264e_vepu2_gen_regs_v2()
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H A Dhal_h264e_vepu1_v2.c301 RK_U32 mb_h = ctx->sps->pic_height_in_mbs; in hal_h264e_vepu1_gen_regs_v2() local
309 mb_h = ctx->sps->pic_width_in_mbs; in hal_h264e_vepu1_gen_regs_v2()
337 val = VEPU_REG_INTRA_AREA_TOP(mb_h) in hal_h264e_vepu1_gen_regs_v2()
338 | VEPU_REG_INTRA_AREA_BOTTOM(mb_h) in hal_h264e_vepu1_gen_regs_v2()
359 if (mb_w * mb_h > 3600) in hal_h264e_vepu1_gen_regs_v2()
374 RK_U32 scaler = MPP_MAX(1, 200 / (mb_w + mb_h)); in hal_h264e_vepu1_gen_regs_v2()
458 val = VEPU_REG_ROI1_TOP_MB(mb_h) in hal_h264e_vepu1_gen_regs_v2()
459 | VEPU_REG_ROI1_BOTTOM_MB(mb_h) in hal_h264e_vepu1_gen_regs_v2()
464 val = VEPU_REG_ROI2_TOP_MB(mb_h) in hal_h264e_vepu1_gen_regs_v2()
465 | VEPU_REG_ROI2_BOTTOM_MB(mb_h) in hal_h264e_vepu1_gen_regs_v2()
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H A Dhal_h264e_vepu_v2.c36 RK_S32 mb_h; member
254 bufs->mb_h = aligned_h >> 4; in h264e_vepu_buf_set_frame_size()
255 if (bufs->mb_h) in h264e_vepu_buf_set_frame_size()
256 bufs->nal_tab_size = MPP_ALIGN((bufs->mb_h + 1) * sizeof(RK_U32), 8); in h264e_vepu_buf_set_frame_size()
524 p->mb_h = MPP_ALIGN(prep->height, 16) / 16; in h264e_vepu_mbrc_setup()
526 p->mbs = p->mb_w * p->mb_h; in h264e_vepu_mbrc_setup()
555 p->check_point_count = MPP_MIN(p->mb_h - 1, VEPU_CHECK_POINTS_MAX); in h264e_vepu_mbrc_setup()
H A Dhal_h264e_vepu_v2.h97 RK_S32 mb_h; member
/rockchip-linux_mpp/mpp/codec/rc/
H A Dvp8e_rc.c63 RK_S32 mb_h = MPP_ALIGN(usr_cfg->height, 16) / 16; in rc_model_v2_vp8_hal_start() local
90 p->start_qp = vp8_initial_qp(info->bit_target, mb_w * mb_h * 16 * 16); in rc_model_v2_vp8_hal_start()
H A Drc_model_v2_smt.c956 RK_S32 mb_h = MPP_ALIGN(p->usr_cfg.height, 16) / 16; in rc_model_v2_smt_start() local
960 qp_out_f0 = cal_smt_first_i_start_qp(p->bits_tgt_upper * ratio, mb_w * mb_h); in rc_model_v2_smt_start()
973 mb_w, mb_h, ratio, p->qp_out); in rc_model_v2_smt_start()
H A Drc_model_v2.c719 RK_S32 mb_h = MPP_ALIGN(usr_cfg->height, 16) / 16; in reenc_calc_cbr_ratio() local
768 RK_U32 tar_bpp = target_bit / (mb_w * mb_h); in reenc_calc_cbr_ratio()
1571 RK_S32 mb_h = MPP_ALIGN(usr_cfg->height, 16) / 16; in rc_model_v2_hal_start() local
1611 info->quality_target = cal_first_i_start_qp(info->bit_target, mb_w * mb_h); in rc_model_v2_hal_start()
/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu541_common.c41 RK_S32 mb_h = MPP_ALIGN(h, 16) / 16; in vepu541_set_one_roi() local
60 pos_y_end = MPP_MIN(pos_y_end, mb_h); in vepu541_set_one_roi()
96 RK_S32 mb_h = MPP_ALIGN(h, 16) / 16; in vepu541_set_roi() local
98 RK_S32 stride_v = MPP_ALIGN(mb_h, 4); in vepu541_set_roi()
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu580_tune.c343 RK_S32 mb_h = MPP_ALIGN(ctx->cfg->prep.height, 16) / 16; in setup_vepu580_qpmap_buf() local
345 = mb_w * mb_h * 8; in setup_vepu580_qpmap_buf()
347 = mb_w * mb_h * 2; in setup_vepu580_qpmap_buf()
349 = mb_w * mb_h; in setup_vepu580_qpmap_buf()
H A Dhal_h264e_vepu510_tune.c142 RK_U32 mb_h = ctx->sps->pic_height_in_mbs; in vepu510_h264e_tune_stat_update() local
143 RK_U32 b16_num = mb_w * mb_h; in vepu510_h264e_tune_stat_update()
H A Dhal_h264e_vepu580.c1252 RK_S32 mb_h = sps->pic_height_in_mbs; in setup_vepu580_rc_base() local
1257 RK_S32 mb_target_bits_mul_16 = (rc_info->bit_target << 4) / (mb_w * mb_h); in setup_vepu580_rc_base()
1439 RK_S32 mb_h = MPP_ALIGN(h, 16) / 16; in vepu580_h264_set_one_roi() local
1458 pos_y_end = MPP_MIN(pos_y_end, mb_h); in vepu580_h264_set_one_roi()
1487 RK_U32 mb_h = ctx->sps->pic_height_in_mbs; in setup_vepu580_intra_refresh() local
1489 RK_U32 h = mb_h * 16; in setup_vepu580_intra_refresh()
1493 RK_U32 stride_v = MPP_ALIGN(mb_h, 4); in setup_vepu580_intra_refresh()
1582 RK_U32 mb_h = MPP_ALIGN(ctx->cfg->prep.height, 64) / 16; in setup_vepu580_roi() local
1583 RK_U32 base_cfg_size = mb_w * mb_h * 8; in setup_vepu580_roi()
1584 RK_U32 qp_cfg_size = mb_w * mb_h * 2; in setup_vepu580_roi()
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H A Dhal_h264e_vepu511.c1162 RK_S32 mb_h = sps->pic_height_in_mbs; in setup_vepu511_rc_base() local
1166 RK_S32 mb_target_bits_mul_16 = (rc_info->bit_target << 4) / (mb_w * mb_h); in setup_vepu511_rc_base()
1366 RK_S32 mb_h = MPP_ALIGN(h, 16) / 16; in vepu511_h264_set_one_roi() local
1385 pos_y_end = MPP_MIN(pos_y_end, mb_h); in vepu511_h264_set_one_roi()
1414 RK_U32 mb_h = ctx->sps->pic_height_in_mbs; in setup_vepu511_intra_refresh() local
1416 RK_U32 h = mb_h * 16; in setup_vepu511_intra_refresh()
1421 RK_U32 stride_v = MPP_ALIGN(mb_h, 4); in setup_vepu511_intra_refresh()
1576 RK_U32 mb_h = MPP_ALIGN(enc_cfg->prep.height, 16) / 16; in setup_vepu511_split() local
1577 RK_U32 slice_num = (mb_w * mb_h + cfg->split_arg - 1) / cfg->split_arg; in setup_vepu511_split()
2451 RK_U32 mb_h = ctx->sps->pic_height_in_mbs; in vepu511_h264e_update_tune_stat() local
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H A Dhal_h264e_vepu510.c1167 RK_S32 mb_h = sps->pic_height_in_mbs; in setup_vepu510_rc_base() local
1172 RK_S32 mb_target_bits_mul_16 = (rc_info->bit_target << 4) / (mb_w * mb_h); in setup_vepu510_rc_base()
1366 RK_S32 mb_h = MPP_ALIGN(h, 16) / 16; in vepu510_h264_set_one_roi() local
1385 pos_y_end = MPP_MIN(pos_y_end, mb_h); in vepu510_h264_set_one_roi()
1414 RK_U32 mb_h = ctx->sps->pic_height_in_mbs; in setup_vepu510_intra_refresh() local
1416 RK_U32 h = mb_h * 16; in setup_vepu510_intra_refresh()
1421 RK_U32 stride_v = MPP_ALIGN(mb_h, 4); in setup_vepu510_intra_refresh()
1576 RK_U32 mb_h = MPP_ALIGN(enc_cfg->prep.height, 16) / 16; in setup_vepu510_split() local
1577 RK_U32 slice_num = (mb_w * mb_h + cfg->split_arg - 1) / cfg->split_arg; in setup_vepu510_split()
2492 RK_U32 mb_h = ctx->sps->pic_height_in_mbs; in hal_h264e_vepu510_ret_task() local
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H A Dhal_h264e_vepu540c.c895 RK_S32 mb_h = sps->pic_height_in_mbs; in setup_vepu540c_rc_base() local
900 RK_S32 mb_target_bits_mul_16 = (rc_info->bit_target << 4) / (mb_w * mb_h); in setup_vepu540c_rc_base()
1136 RK_U32 mb_h = MPP_ALIGN(cfg->prep.height, 16) / 16; in setup_vepu540c_split() local
1137 RK_U32 slice_num = (mb_w * mb_h + cfg->split.split_arg - 1) / cfg->split.split_arg; in setup_vepu540c_split()
1691 RK_U32 mb_h = ctx->sps->pic_height_in_mbs; in hal_h264e_vepu540c_ret_task() local
1692 RK_U32 mbs = mb_w * mb_h; in hal_h264e_vepu540c_ret_task()
H A Dhal_h264e_vepu541.c822 RK_S32 mb_h = sps->pic_height_in_mbs; in setup_vepu541_rc_base() local
827 RK_S32 mb_target_bits_mul_16 = (rc_info->bit_target << 4) / (mb_w * mb_h); in setup_vepu541_rc_base()
1808 RK_U32 mb_h = ctx->sps->pic_height_in_mbs; in hal_h264e_vepu541_ret_task() local
1809 RK_U32 mbs = mb_w * mb_h; in hal_h264e_vepu541_ret_task()
/rockchip-linux_mpp/mpp/hal/vpu/jpege/
H A Dhal_jpege_vepu2_v2.c251 RK_U32 mb_h = MPP_ALIGN(height, 16) / 16; in hal_jpege_vepu2_get_task() local
252 RK_U32 part_rows = MPP_ALIGN(mb_h, 4) / 4; in hal_jpege_vepu2_get_task()
257 RK_U32 ecs_num = (mb_h + syntax->part_rows - 1) / syntax->part_rows; in hal_jpege_vepu2_get_task()
299 part_rows = (mb_h >= part_rows) ? part_rows : mb_h; in hal_jpege_vepu2_get_task()
313 mb_h -= part_rows; in hal_jpege_vepu2_get_task()
/rockchip-linux_mpp/mpp/codec/enc/jpeg/
H A Djpege_api_v2.c259 RK_U32 mb_h = syntax->mcu_ver_cnt; in jpege_proc_hal() local
267 if (part_rows >= mb_h) in jpege_proc_hal()
/rockchip-linux_mpp/mpp/codec/enc/h265/
H A Dh265e_ps.c464 RK_S32 mb_h = (sps->m_picHeightInLumaSamples + sps->m_maxCUSize - 1) / sps->m_maxCUSize; in h265e_set_pps() local
492 pps->m_nTileRowHeightArray[index] = mb_h; in h265e_set_pps()
496 pps->m_nTileRowHeightArray[index] = mb_h; in h265e_set_pps()
H A Dh265e_slice.c859 RK_U32 mb_h; in h265e_code_slice_skip_frame() local
888 mb_h = (sps->m_picHeightInLumaSamples + sps->m_maxCUSize - 1) / sps->m_maxCUSize; in h265e_code_slice_skip_frame()
889 tile.mb_total = mb_wd * mb_h; in h265e_code_slice_skip_frame()
/rockchip-linux_mpp/mpp/codec/enc/h264/
H A Dh264e_slice.h92 RK_S32 mb_h; member
H A Dh264e_slice.c49 slice->mb_h = sps->pic_height_in_mbs; in h264e_slice_update()
947 for (i = 0; i < slice->mb_w * slice->mb_h; i++) { in h264e_slice_write_pskip()
961 mpp_writer_put_ue(s, slice->mb_w * slice->mb_h); in h264e_slice_write_pskip()
963 mpp_writer_bits(s), slice->mb_w * slice->mb_h); in h264e_slice_write_pskip()
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu541.c796 RK_S32 mb_h = MPP_ALIGN(h, 64) / 64; in vepu541_h265_set_roi() local
800 for (j = 0; j < mb_h; j++) { in vepu541_h265_set_roi()
1641 RK_S32 mb_h = MPP_ALIGN(syn->pp.pic_height, 64) / 64; in hal_h265e_v540_set_uniform_tile() local
1645 regs->tile_cfg.tile_height_m1 = mb_h - 1; in hal_h265e_v540_set_uniform_tile()
H A Dhal_h265e_vepu580.c2643 RK_U32 mb_h = MPP_ALIGN(enc_cfg->prep.height, 64) / 64; in vepu580_setup_split() local
2649 slice_num = (mb_w * mb_h + cfg->split_arg - 1) / cfg->split_arg; in vepu580_setup_split()
2814 RK_S32 mb_h = MPP_ALIGN(syn->pp.pic_height, 64) / 64; in hal_h265e_v580_set_uniform_tile() local
2845 regs->reg0252_tile_cfg.tile_h_m1 = mb_h - 1; in hal_h265e_v580_set_uniform_tile()

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