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Searched refs:fd_ref0 (Results 1 – 6 of 6) sorted by relevance

/rockchip-linux_mpp/mpp/hal/vpu/mpg4d/
H A Dhal_m4vd_vdpu2.c152 mpp_assert(ctx->fd_ref0 >= 0); in vdpu2_mpg4d_setup_regs_by_syntax()
153 if (ctx->fd_ref0 >= 0) { in vdpu2_mpg4d_setup_regs_by_syntax()
154 regs->reg134_ref2_base = (RK_U32)ctx->fd_ref0; in vdpu2_mpg4d_setup_regs_by_syntax()
155 regs->reg135_ref3_base = (RK_U32)ctx->fd_ref0; in vdpu2_mpg4d_setup_regs_by_syntax()
175 if (ctx->fd_ref0 >= 0) { in vdpu2_mpg4d_setup_regs_by_syntax()
176 regs->reg131_ref0_base = (RK_U32)ctx->fd_ref0; in vdpu2_mpg4d_setup_regs_by_syntax()
177 regs->reg148_ref1_base = (RK_U32)ctx->fd_ref0; in vdpu2_mpg4d_setup_regs_by_syntax()
381 ctx->fd_ref0 = (buf_frm_ref0) ? (mpp_buffer_get_fd(buf_frm_ref0)) : (-1); in vdpu2_mpg4d_gen_regs()
H A Dhal_m4vd_vdpu1.c154 mpp_assert(ctx->fd_ref0 >= 0); in vdpu1_mpg4d_setup_regs_by_syntax()
155 if (ctx->fd_ref0 >= 0) { in vdpu1_mpg4d_setup_regs_by_syntax()
156 regs->SwReg16.sw_refer2_base = (RK_U32)ctx->fd_ref0; in vdpu1_mpg4d_setup_regs_by_syntax()
157 regs->SwReg17.sw_refer3_base = (RK_U32)ctx->fd_ref0; in vdpu1_mpg4d_setup_regs_by_syntax()
177 if (ctx->fd_ref0 >= 0) { in vdpu1_mpg4d_setup_regs_by_syntax()
178 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_ref0; in vdpu1_mpg4d_setup_regs_by_syntax()
179 regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_ref0; in vdpu1_mpg4d_setup_regs_by_syntax()
383 ctx->fd_ref0 = (buf_frm_ref0) ? (mpp_buffer_get_fd(buf_frm_ref0)) : (-1); in vdpu1_mpg4d_gen_regs()
H A Dhal_m4vd_com.h40 RK_S32 fd_ref0; member
/rockchip-linux_mpp/mpp/hal/vpu/h263d/
H A Dhal_h263d_vdpu2.c99 if (ctx->fd_ref0 >= 0) { in vpu2_h263d_setup_regs_by_syntax()
100 regs->reg131_ref0_base = (RK_U32)ctx->fd_ref0; in vpu2_h263d_setup_regs_by_syntax()
101 regs->reg148_ref1_base = (RK_U32)ctx->fd_ref0; in vpu2_h263d_setup_regs_by_syntax()
223 ctx->fd_ref0 = (buf_frm_ref0) ? (mpp_buffer_get_fd(buf_frm_ref0)) : (-1); in hal_vpu2_h263d_gen_regs()
H A Dhal_h263d_vdpu1.c98 if (ctx->fd_ref0 >= 0) { in vpu1_h263d_setup_regs_by_syntax()
99 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_ref0; in vpu1_h263d_setup_regs_by_syntax()
100 regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_ref0; in vpu1_h263d_setup_regs_by_syntax()
222 ctx->fd_ref0 = (buf_frm_ref0) ? (mpp_buffer_get_fd(buf_frm_ref0)) : (-1); in hal_vpu1_h263d_gen_regs()
H A Dhal_h263d_base.h32 RK_S32 fd_ref0; member