Searched refs:dmsr_edge_th_high_arr (Results 1 – 4 of 4) sorted by relevance
141 p_dmsr_param->dmsr_edge_th_high_arr[0] = 60; in vdpp_set_default_dmsr_param()142 p_dmsr_param->dmsr_edge_th_high_arr[1] = 40; in vdpp_set_default_dmsr_param()143 p_dmsr_param->dmsr_edge_th_high_arr[2] = 20; in vdpp_set_default_dmsr_param()144 p_dmsr_param->dmsr_edge_th_high_arr[3] = 10; in vdpp_set_default_dmsr_param()145 p_dmsr_param->dmsr_edge_th_high_arr[4] = 10; in vdpp_set_default_dmsr_param()146 p_dmsr_param->dmsr_edge_th_high_arr[5] = 10; in vdpp_set_default_dmsr_param()147 p_dmsr_param->dmsr_edge_th_high_arr[6] = 10; in vdpp_set_default_dmsr_param()
670 dmsr->reg0.sw_dmsr_edge_high_thre_0 = p_dmsr_param->dmsr_edge_th_high_arr[0]; in set_dmsr_to_vdpp_reg()674 dmsr->reg1.sw_dmsr_edge_high_thre_1 = p_dmsr_param->dmsr_edge_th_high_arr[1]; in set_dmsr_to_vdpp_reg()678 dmsr->reg2.sw_dmsr_edge_high_thre_2 = p_dmsr_param->dmsr_edge_th_high_arr[2]; in set_dmsr_to_vdpp_reg()682 dmsr->reg3.sw_dmsr_edge_high_thre_3 = p_dmsr_param->dmsr_edge_th_high_arr[3]; in set_dmsr_to_vdpp_reg()686 dmsr->reg4.sw_dmsr_edge_high_thre_4 = p_dmsr_param->dmsr_edge_th_high_arr[4]; in set_dmsr_to_vdpp_reg()690 dmsr->reg5.sw_dmsr_edge_high_thre_5 = p_dmsr_param->dmsr_edge_th_high_arr[5]; in set_dmsr_to_vdpp_reg()694 dmsr->reg6.sw_dmsr_edge_high_thre_6 = p_dmsr_param->dmsr_edge_th_high_arr[6]; in set_dmsr_to_vdpp_reg()703 … tmp_diff = p_dmsr_param->dmsr_edge_th_high_arr[i] - p_dmsr_param->dmsr_edge_th_low_arr[i]; in set_dmsr_to_vdpp_reg()
1222 p_dmsr_param->dmsr_edge_th_high_arr[0] = 60; in vdpp2_set_default_dmsr_param()1223 p_dmsr_param->dmsr_edge_th_high_arr[1] = 40; in vdpp2_set_default_dmsr_param()1224 p_dmsr_param->dmsr_edge_th_high_arr[2] = 20; in vdpp2_set_default_dmsr_param()1225 p_dmsr_param->dmsr_edge_th_high_arr[3] = 10; in vdpp2_set_default_dmsr_param()1226 p_dmsr_param->dmsr_edge_th_high_arr[4] = 10; in vdpp2_set_default_dmsr_param()1227 p_dmsr_param->dmsr_edge_th_high_arr[5] = 10; in vdpp2_set_default_dmsr_param()1228 p_dmsr_param->dmsr_edge_th_high_arr[6] = 10; in vdpp2_set_default_dmsr_param()
60 RK_U32 dmsr_edge_th_high_arr[7]; member