Searched refs:cudecis_thd0 (Results 1 – 4 of 4) sorted by relevance
644 reg->cudecis_thd0.base_thre_rough_mad32_intra = 9; in vepu510_h265_rdo_cfg()645 reg->cudecis_thd0.delta0_thre_rough_mad32_intra = 10; in vepu510_h265_rdo_cfg()646 reg->cudecis_thd0.delta1_thre_rough_mad32_intra = 55; in vepu510_h265_rdo_cfg()647 reg->cudecis_thd0.delta2_thre_rough_mad32_intra = 55; in vepu510_h265_rdo_cfg()648 reg->cudecis_thd0.delta3_thre_rough_mad32_intra = 66; in vepu510_h265_rdo_cfg()649 reg->cudecis_thd0.delta4_thre_rough_mad32_intra_low5 = 2; in vepu510_h265_rdo_cfg()
1767 reg_rc->cudecis_thd0.base_thre_rough_mad32_intra = 9; in vepu511_h265_set_rdo_regs()1768 reg_rc->cudecis_thd0.delta0_thre_rough_mad32_intra = 10; in vepu511_h265_set_rdo_regs()1769 reg_rc->cudecis_thd0.delta1_thre_rough_mad32_intra = 55; in vepu511_h265_set_rdo_regs()1770 reg_rc->cudecis_thd0.delta2_thre_rough_mad32_intra = 55; in vepu511_h265_set_rdo_regs()1771 reg_rc->cudecis_thd0.delta3_thre_rough_mad32_intra = 66; in vepu511_h265_set_rdo_regs()1772 reg_rc->cudecis_thd0.delta4_thre_rough_mad32_intra_low5 = 2; in vepu511_h265_set_rdo_regs()
678 } cudecis_thd0; member
1294 } cudecis_thd0; member