Searched refs:H265H_DBG_REG (Results 1 – 6 of 6) sorted by relevance
| /rockchip-linux_mpp/mpp/hal/rkdec/h265d/ |
| H A D | hal_h265d_debug.h | 26 #define H265H_DBG_REG (0x00000008) macro
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| H A D | hal_h265d_rkv.c | 947 if (hal_h265d_debug & H265H_DBG_REG) { in hal_h265d_rkv_start()
949 … h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n", i, ((RK_U32 *)hw_regs)[i]); in hal_h265d_rkv_start()
1042 if (hal_h265d_debug & H265H_DBG_REG) { in hal_h265d_rkv_wait()
1043 …h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[1]=0x%08X, regs[45]=0x%08x\n", ((RK_U32 *)hw_regs)[1],… in hal_h265d_rkv_wait()
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| H A D | hal_h265d_vdpu382.c | 975 h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n", in hal_h265d_vdpu382_start()
1138 h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n", in hal_h265d_vdpu382_wait()
1143 h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n", in hal_h265d_vdpu382_wait()
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| H A D | hal_h265d_vdpu384a.c | 1200 h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n", in hal_h265d_vdpu384a_start()
1342 h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n", in hal_h265d_vdpu384a_wait()
1347 h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n", in hal_h265d_vdpu384a_wait()
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| H A D | hal_h265d_vdpu34x.c | 1182 h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n", in hal_h265d_vdpu34x_start()
1348 h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n", in hal_h265d_vdpu34x_wait()
1353 h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n", in hal_h265d_vdpu34x_wait()
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| H A D | hal_h265d_vdpu383.c | 1262 h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n", in hal_h265d_vdpu383_start()
1404 h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n", in hal_h265d_vdpu383_wait()
1409 h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n", in hal_h265d_vdpu383_wait()
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