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Searched refs:tRP (Results 1 – 9 of 9) sorted by relevance

/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.h13 unsigned int tRP; /* ND_nRE pulse width */ member
H A Dpxa3xx_nand.c433 NDTR0_tRP(ns2cycle(t->tRP, nand_clk)); in pxa3xx_nand_set_timing()
/rk3399_rockchip-uboot/doc/device-tree-bindings/nand/
H A Dnvidia,tegra20-nand.txt33 non-EDO mode: Max(tRP, tREA) + 6ns
34 EDO mode: tRP timing
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c130 u32 tRP; /* in ps */ member
381 const u32 tRP = PS2CYCLES_ROUNDUP(para->tRP); in mctl_channel_init() local
552 (MCTL_DIV2(tRRD) << 8) | (MCTL_DIV2(tRP) << 0), in mctl_channel_init()
645 (tRCD << 12) | (tRP << 8) | (tWTR << 4) | (tRTP << 0), in mctl_channel_init()
892 .tRP = 13750, in sunxi_dram_init()
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt51 rockchip,trp: tRP,AC timing parameters from the memory data-sheet
/rk3399_rockchip-uboot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg59 # bit11-8: 4, 5 cyle tRP
H A Dkwbimage-lsxhl.cfg59 # bit11-8: 4, 5 cyle tRP
/rk3399_rockchip-uboot/board/d-link/dns325/
H A Dkwbimage.cfg56 # bit11-8: 4, 5 cyle tRP
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dam43x-epos-evm.dts590 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */