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Searched refs:status_bit (Results 1 – 5 of 5) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.h147 u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */ member
178 .status_bit = (_status_bit), \
190 .status_bit = (_status_bit), \
201 .status_bit = (_status_bit), \
212 .status_bit = (_status_bit), \
222 .status_bit = (_status_bit), \
H A Dclk-core.c139 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); in peri_clk_enable()
151 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); in peri_clk_enable()
349 if (!!(reg & (1 << cd->gate.status_bit)) == !!enable) in bus_clk_enable()
362 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, in bus_clk_enable()
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.h147 u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */ member
178 .status_bit = (_status_bit), \
190 .status_bit = (_status_bit), \
201 .status_bit = (_status_bit), \
212 .status_bit = (_status_bit), \
222 .status_bit = (_status_bit), \
H A Dclk-core.c139 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); in peri_clk_enable()
151 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); in peri_clk_enable()
349 if (!!(reg & (1 << cd->gate.status_bit)) == !!enable) in bus_clk_enable()
362 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, in bus_clk_enable()
/rk3399_rockchip-uboot/drivers/mmc/
H A Dsunxi_mmc.c274 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY : in mmc_trans_data_by_cpu() local
287 while (readl(&priv->reg->status) & status_bit) { in mmc_trans_data_by_cpu()