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Searched refs:rk628 (Results 1 – 23 of 23) sorted by relevance

/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_rgb.c13 int rk628_rgbrx_parse(struct rk628 *rk628) in rk628_rgbrx_parse() argument
16 if ((rk628_input_is_bt1120(rk628) || rk628_output_is_bt1120(rk628)) && in rk628_rgbrx_parse()
17 dev_read_bool(rk628->dev, "bt1120-dual-edge")) in rk628_rgbrx_parse()
18 rk628->rgb.bt1120_dual_edge = true; in rk628_rgbrx_parse()
21 if (rk628_input_is_bt1120(rk628)) { in rk628_rgbrx_parse()
22 if (dev_read_bool(rk628->dev, "bt1120-yc-swap")) in rk628_rgbrx_parse()
23 rk628->rgb.bt1120_yc_swap = true; in rk628_rgbrx_parse()
25 if (dev_read_bool(rk628->dev, "bt1120-uv-swap")) in rk628_rgbrx_parse()
26 rk628->rgb.bt1120_uv_swap = true; in rk628_rgbrx_parse()
33 int rk628_rgbtx_parse(struct rk628 *rk628, ofnode rgb_np) in rk628_rgbtx_parse() argument
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H A Drk628.c17 static int rk628_power_on(struct rk628 *rk628) in rk628_power_on() argument
19 if (rk628->power_supply) in rk628_power_on()
20 regulator_set_enable(rk628->power_supply, 1); in rk628_power_on()
22 if (dm_gpio_is_valid(&rk628->enable_gpio)) { in rk628_power_on()
23 dm_gpio_set_value(&rk628->enable_gpio, 1); in rk628_power_on()
27 if (dm_gpio_is_valid(&rk628->reset_gpio)) { in rk628_power_on()
28 dm_gpio_set_value(&rk628->reset_gpio, 0); in rk628_power_on()
30 dm_gpio_set_value(&rk628->reset_gpio, 1); in rk628_power_on()
32 dm_gpio_set_value(&rk628->reset_gpio, 0); in rk628_power_on()
37 rk628_i2c_write(rk628, GRF_GPIO3AB_SEL_CON, 0x30002000); in rk628_power_on()
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H A Drk628_dsi.c203 static inline int dsi_write(struct rk628 *rk628, const struct rk628_dsi *dsi, in dsi_write() argument
210 return rk628_i2c_write(rk628, dsi_base + reg, val); in dsi_write()
213 static inline int dsi_read(struct rk628 *rk628, const struct rk628_dsi *dsi, in dsi_read() argument
220 return rk628_i2c_read(rk628, dsi_base + reg, val); in dsi_read()
223 static inline int dsi_update_bits(struct rk628 *rk628, in dsi_update_bits() argument
231 return rk628_i2c_update_bits(rk628, dsi_base + reg, mask, val); in dsi_update_bits()
234 int rk628_dsi_parse(struct rk628 *rk628, ofnode dsi_np) in rk628_dsi_parse() argument
242 rk628->dsi0.id = 0; in rk628_dsi_parse()
243 rk628->dsi0.channel = 0; in rk628_dsi_parse()
244 rk628->dsi0.rk628 = rk628; in rk628_dsi_parse()
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H A Drk628_cru.c58 static unsigned long rk628_cru_clk_get_rate_pll(struct rk628 *rk628, in rk628_cru_clk_get_rate_pll() argument
67 if (id == CGU_CLK_APLL && rk628->version < RK628F_VERSION) in rk628_cru_clk_get_rate_pll()
70 rk628_i2c_read(rk628, CRU_MODE_CON00, &val); in rk628_cru_clk_get_rate_pll()
94 rk628_i2c_read(rk628, offset + CRU_CPLL_CON0, &con0); in rk628_cru_clk_get_rate_pll()
95 rk628_i2c_read(rk628, offset + CRU_CPLL_CON1, &con1); in rk628_cru_clk_get_rate_pll()
96 rk628_i2c_read(rk628, offset + CRU_CPLL_CON2, &con2); in rk628_cru_clk_get_rate_pll()
126 static unsigned long rk628_cru_clk_set_rate_pll(struct rk628 *rk628, in rk628_cru_clk_set_rate_pll() argument
158 rk628_i2c_write(rk628, offset + CRU_CPLL_CON1, PLL_PD(1)); in rk628_cru_clk_set_rate_pll()
161 rk628_i2c_write(rk628, offset + CRU_CPLL_CON0, PLL_BYPASS(1)); in rk628_cru_clk_set_rate_pll()
162 rk628_i2c_write(rk628, offset + CRU_CPLL_CON1, PLL_PD(0)); in rk628_cru_clk_set_rate_pll()
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H A Drk628_gvi.c20 int rk628_gvi_parse(struct rk628 *rk628, ofnode gvi_np) in rk628_gvi_parse() argument
30 rk628->gvi.lanes = val; in rk628_gvi_parse()
33 rk628->gvi.division_mode = true; in rk628_gvi_parse()
35 rk628->gvi.division_mode = false; in rk628_gvi_parse()
38 rk628->gvi.frm_rst = true; in rk628_gvi_parse()
40 rk628->gvi.frm_rst = false; in rk628_gvi_parse()
45 rk628->gvi.bus_format = GVI_MEDIA_BUS_FMT_RGB666_1X18; in rk628_gvi_parse()
47 rk628->gvi.bus_format = GVI_MEDIA_BUS_FMT_RGB101010_1X30; in rk628_gvi_parse()
49 rk628->gvi.bus_format = GVI_MEDIA_BUS_FMT_YUYV8_1X16; in rk628_gvi_parse()
51 rk628->gvi.bus_format = GVI_MEDIA_BUS_FMT_YUYV10_1X20; in rk628_gvi_parse()
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H A Drk628_lvds.c13 static inline void lvds_write(struct rk628 *rk628, u32 reg, u32 val) in lvds_write() argument
15 rk628_i2c_write(rk628, reg, val); in lvds_write()
18 static inline void lvds_update_bits(struct rk628 *rk628, u32 reg, in lvds_update_bits() argument
21 rk628_i2c_update_bits(rk628, reg, mask, val); in lvds_update_bits()
24 int rk628_lvds_parse(struct rk628 *rk628, ofnode lvds_np) in rk628_lvds_parse() argument
34 rk628->lvds.format = LVDS_FORMAT_JEIDA_24BIT; in rk628_lvds_parse()
36 rk628->lvds.format = LVDS_FORMAT_JEIDA_18BIT; in rk628_lvds_parse()
38 rk628->lvds.format = LVDS_FORMAT_VESA_18BIT; in rk628_lvds_parse()
40 rk628->lvds.format = LVDS_FORMAT_VESA_24BIT; in rk628_lvds_parse()
44 rk628->lvds.link_type = LVDS_DUAL_LINK_ODD_EVEN_PIXELS; in rk628_lvds_parse()
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H A Drk628_hdmirx.c18 struct rk628 *rk628 = hdmirx->parent; in hdmirx_phy_write() local
20 rk628_i2c_write(rk628, HDMI_RX_I2CM_PHYG3_ADDRESS, offset); in hdmirx_phy_write()
21 rk628_i2c_write(rk628, HDMI_RX_I2CM_PHYG3_DATAO, val); in hdmirx_phy_write()
22 rk628_i2c_write(rk628, HDMI_RX_I2CM_PHYG3_OPERATION, 1); in hdmirx_phy_write()
25 static void rk628_hdmirx_reset_control_assert(struct rk628 *rk628) in rk628_hdmirx_reset_control_assert() argument
28 rk628_i2c_write(rk628, CRU_SOFTRST_CON02, 0x40004); in rk628_hdmirx_reset_control_assert()
30 rk628_i2c_write(rk628, CRU_SOFTRST_CON02, 0x10001000); in rk628_hdmirx_reset_control_assert()
33 static void rk628_hdmirx_reset_control_deassert(struct rk628 *rk628) in rk628_hdmirx_reset_control_deassert() argument
36 rk628_i2c_write(rk628, CRU_SOFTRST_CON02, 0x40000); in rk628_hdmirx_reset_control_deassert()
38 rk628_i2c_write(rk628, CRU_SOFTRST_CON02, 0x10000000); in rk628_hdmirx_reset_control_deassert()
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H A Drk628_combtxphy.c22 static void rk628_combtxphy_dsi_power_on(struct rk628 *rk628) in rk628_combtxphy_dsi_power_on() argument
24 struct rk628_combtxphy *combtxphy = &rk628->combtxphy; in rk628_combtxphy_dsi_power_on()
28 rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_BUS_WIDTH_MASK | in rk628_combtxphy_dsi_power_on()
33 rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, in rk628_combtxphy_dsi_power_on()
37 rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, in rk628_combtxphy_dsi_power_on()
40 rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_PD_PLL, SW_PD_PLL); in rk628_combtxphy_dsi_power_on()
43 rk628_i2c_update_bits(rk628, COMBTXPHY_CON8, SW_SSC_DEPTH_MASK | SW_SSC_EN_MASK, in rk628_combtxphy_dsi_power_on()
46 rk628_i2c_write(rk628, COMBTXPHY_CON5, in rk628_combtxphy_dsi_power_on()
52 rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_PD_PLL, 0); in rk628_combtxphy_dsi_power_on()
54 ret = rk628_read_poll_timeout(rk628, GRF_DPHY0_STATUS, val, in rk628_combtxphy_dsi_power_on()
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H A Drk628_rgb.h12 int rk628_rgbrx_parse(struct rk628 *rk628);
13 int rk628_rgbtx_parse(struct rk628 *rk628, ofnode rgb_np);
14 void rk628_rgb_rx_enable(struct rk628 *rk628);
15 void rk628_rgb_tx_enable(struct rk628 *rk628);
16 void rk628_rgb_tx_disable(struct rk628 *rk628);
17 void rk628_bt1120_rx_enable(struct rk628 *rk628);
18 void rk628_bt1120_tx_enable(struct rk628 *rk628);
H A Dpanel.h12 int rk628_panel_info_get(struct rk628 *rk628, ofnode np);
13 void rk628_panel_prepare(struct rk628 *rk628);
14 void rk628_panel_enable(struct rk628 *rk628);
15 void rk628_panel_unprepare(struct rk628 *rk628);
16 void rk628_panel_disable(struct rk628 *rk628);
H A Dpanel.c103 static int dsi_panel_get_cmds(struct rk628 *rk628, ofnode dsi_np) in dsi_panel_get_cmds() argument
116 rk628->panel->on_cmds = kcalloc(1, sizeof(struct panel_cmds), GFP_KERNEL); in dsi_panel_get_cmds()
117 if (!rk628->panel->on_cmds) in dsi_panel_get_cmds()
120 err = dsi_panel_parse_cmds(data, len, rk628->panel->on_cmds); in dsi_panel_get_cmds()
130 rk628->panel->off_cmds = kcalloc(1, sizeof(struct panel_cmds), GFP_KERNEL); in dsi_panel_get_cmds()
131 if (!rk628->panel->off_cmds) { in dsi_panel_get_cmds()
136 err = dsi_panel_parse_cmds(data, len, rk628->panel->off_cmds); in dsi_panel_get_cmds()
147 kfree(rk628->panel->off_cmds); in dsi_panel_get_cmds()
149 kfree(rk628->panel->on_cmds->cmds); in dsi_panel_get_cmds()
150 kfree(rk628->panel->on_cmds->buf); in dsi_panel_get_cmds()
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H A Drk628.h449 struct rk628 *rk628; member
501 struct rk628 *parent;
510 struct rk628 { struct
534 static inline bool rk628_input_is_hdmi(struct rk628 *rk628) in rk628_input_is_hdmi() argument
536 return rk628->input_mode & BIT(INPUT_MODE_HDMI); in rk628_input_is_hdmi()
539 static inline bool rk628_input_is_rgb(struct rk628 *rk628) in rk628_input_is_rgb() argument
541 return rk628->input_mode & BIT(INPUT_MODE_RGB); in rk628_input_is_rgb()
544 static inline bool rk628_input_is_bt1120(struct rk628 *rk628) in rk628_input_is_bt1120() argument
546 return rk628->input_mode & BIT(INPUT_MODE_BT1120); in rk628_input_is_bt1120()
549 static inline bool rk628_output_is_rgb(struct rk628 *rk628) in rk628_output_is_rgb() argument
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H A Drk628_post_process.h11 void rk628_post_process_init(struct rk628 *rk628);
12 void rk628_post_process_enable(struct rk628 *rk628);
13 void rk628_post_process_disable(struct rk628 *rk628);
H A Drk628_lvds.h11 int rk628_lvds_parse(struct rk628 *rk628, ofnode lvds_np);
12 void rk628_lvds_enable(struct rk628 *rk628);
13 void rk628_lvds_disable(struct rk628 *rk628);
H A Drk628_combtxphy.h88 void rk628_combtxphy_set_gvi_division_mode(struct rk628 *rk628, bool division);
89 void rk628_combtxphy_set_mode(struct rk628 *rk628, enum rk628_phy_mode mode);
90 void rk628_combtxphy_set_bus_width(struct rk628 *rk628, uint32_t bus_width);
91 uint32_t rk628_combtxphy_get_bus_width(struct rk628 *rk628);
92 void rk628_combtxphy_power_on(struct rk628 *rk628);
93 void rk628_combtxphy_power_off(struct rk628 *rk628);
H A Drk628_post_process.c1324 static void rk628_post_process_scaler_init(struct rk628 *rk628, in rk628_post_process_scaler_init() argument
1342 if (rk628->version == RK628F_VERSION && rk628->gvi.division_mode) in rk628_post_process_scaler_init()
1420 rk628_i2c_update_bits(rk628, GRF_RGB_DEC_CON0, SW_HRES_MASK, in rk628_post_process_scaler_init()
1422 rk628_i2c_write(rk628, GRF_SCALER_CON0, SCL_VER_DOWN_MODE(ver_down_mode) | in rk628_post_process_scaler_init()
1426 rk628_i2c_write(rk628, GRF_SCALER_CON1, SCL_V_FACTOR(scl_v_factor) | in rk628_post_process_scaler_init()
1428 rk628_i2c_write(rk628, GRF_SCALER_CON2, DSP_FRAME_VST(dsp_frame_vst) | in rk628_post_process_scaler_init()
1430 rk628_i2c_write(rk628, GRF_SCALER_CON3, DSP_HS_END(dsp_hs_end) | in rk628_post_process_scaler_init()
1432 rk628_i2c_write(rk628, GRF_SCALER_CON4, DSP_HACT_END(dsp_hact_end) | in rk628_post_process_scaler_init()
1434 rk628_i2c_write(rk628, GRF_SCALER_CON5, DSP_VS_END(dsp_vs_end) | in rk628_post_process_scaler_init()
1436 rk628_i2c_write(rk628, GRF_SCALER_CON6, DSP_VACT_END(dsp_vact_end) | in rk628_post_process_scaler_init()
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H A Drk628_dsi.h154 int rk628_dsi_parse(struct rk628 *rk628, ofnode dsi_np);
155 void rk628_mipi_dsi_pre_enable(struct rk628 *rk628);
156 void rk628_mipi_dsi_enable(struct rk628 *rk628);
157 void rk628_dsi_disable(struct rk628 *rk628);
158 void rk628_mipi_dsi_create_debugfs_file(struct rk628 *rk628);
H A Drk628_hdmitx.h353 void rk628_hdmitx_disable(struct rk628 *rk628);
354 int rk628_hdmitx_enable(struct rk628 *rk628);
355 void rk628_hdmitx_create_debugfs_file(struct rk628 *rk628);
357 static inline void rk628_hdmitx_disable(struct rk628 *rk628) in rk628_hdmitx_disable() argument
361 static inline int rk628_hdmitx_enable(struct rk628 *rk628) in rk628_hdmitx_enable() argument
366 static inline void rk628_hdmitx_create_debugfs_file(struct rk628 *rk628) in rk628_hdmitx_create_debugfs_file() argument
H A Drk628_cru.h176 unsigned long rk628_cru_clk_get_rate(struct rk628 *rk628, unsigned int id);
177 int rk628_cru_clk_set_rate(struct rk628 *rk628, unsigned int id,
179 void rk628_cru_init(struct rk628 *rk628);
H A Drk628_gvi.h216 int rk628_gvi_parse(struct rk628 *rk628, ofnode gvi_np);
217 void rk628_gvi_enable(struct rk628 *rk628);
218 void rk628_gvi_disable(struct rk628 *rk628);
H A DMakefile1 obj-y += rk628.o rk628_cru.o rk628_hdmirx.o rk628_post_process.o \
H A Drk628_hdmirx.h632 int rk628_hdmirx_enable(struct rk628 *rk628);
/rk3399_rockchip-uboot/drivers/video/drm/
H A DMakefile39 obj-$(CONFIG_DRM_ROCKCHIP_RK628) += rk628/