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Searched refs:rk3128_pll_clks (Results 1 – 1 of 1) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3128.c80 static struct rockchip_pll_clock rk3128_pll_clks[] = { variable
108 old_rate = rockchip_pll_get_rate(&rk3128_pll_clks[APLL], in rk3128_armclk_set_clk()
111 if (rockchip_pll_set_rate(&rk3128_pll_clks[APLL], in rk3128_armclk_set_clk()
131 if (rockchip_pll_set_rate(&rk3128_pll_clks[APLL], in rk3128_armclk_set_clk()
136 return rockchip_pll_get_rate(&rk3128_pll_clks[APLL], priv->cru, APLL); in rk3128_armclk_set_clk()
455 rockchip_pll_set_rate(&rk3128_pll_clks[CPLL], in rk3128_vop_set_clk()
490 parent = rockchip_pll_get_rate(&rk3128_pll_clks[CPLL], in rk3128_vop_get_rate()
539 rate = rockchip_pll_get_rate(&rk3128_pll_clks[clk->id - 1], in rk3128_clk_get_rate()
543 rate = rockchip_pll_get_rate(&rk3128_pll_clks[APLL], in rk3128_clk_get_rate()
602 ret = rockchip_pll_set_rate(&rk3128_pll_clks[clk->id - 1], in rk3128_clk_set_rate()
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