| /rk3399_rockchip-uboot/arch/arm/mach-socfpga/ |
| H A D | freeze_controller.c | 31 u32 reg_value; in sys_mgr_frzctrl_freeze_req() local
83 reg_value = readl(&freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
87 reg_value in sys_mgr_frzctrl_freeze_req()
88 = (reg_value & ~reg_cfg_mask) in sys_mgr_frzctrl_freeze_req()
91 writel(reg_value, &freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
97 reg_value = readl(&freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
98 reg_value in sys_mgr_frzctrl_freeze_req()
99 = (reg_value & in sys_mgr_frzctrl_freeze_req()
102 writel(reg_value, &freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
113 u32 reg_value; in sys_mgr_frzctrl_thaw_req() local
[all …]
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rk3399.c | 208 u32 reg_value; in phy_io_config() local
295 reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq; in phy_io_config()
297 clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8); in phy_io_config()
299 clrsetbits_le32(&denali_phy[914], 0xfff, reg_value); in phy_io_config()
301 clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16); in phy_io_config()
303 clrsetbits_le32(&denali_phy[915], 0xfff, reg_value); in phy_io_config()
305 reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac; in phy_io_config()
307 clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); in phy_io_config()
330 reg_value = ((boostp << 4) | boostn); in phy_io_config()
332 clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8); in phy_io_config()
[all …]
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| /rk3399_rockchip-uboot/drivers/net/phy/ |
| H A D | cortina.c | 213 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & in cs4340_upload_firmware()
215 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); in cs4340_upload_firmware()
222 int reg_value; in cs4340_phy_init() local
229 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); in cs4340_phy_init()
230 if (reg_value & mseq_edc_bist_done) { in cs4340_phy_init()
231 if (0 == (reg_value & mseq_edc_bist_fail)) in cs4340_phy_init()
244 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); in cs4340_phy_init()
245 if (reg_value) { in cs4340_phy_init()
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| /rk3399_rockchip-uboot/drivers/usb/musb-new/ |
| H A D | sunxi.c | 163 u32 reg_value; in USBC_ConfigFIFO_Base() local
166 reg_value = readl(SUNXI_SRAMC_BASE + 0x04); in USBC_ConfigFIFO_Base()
167 reg_value &= ~(0x03 << 0); in USBC_ConfigFIFO_Base()
168 reg_value |= (1 << 0); in USBC_ConfigFIFO_Base()
169 writel(reg_value, SUNXI_SRAMC_BASE + 0x04); in USBC_ConfigFIFO_Base()
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| /rk3399_rockchip-uboot/drivers/video/sunxi/ |
| H A D | sunxi_de2.c | 36 u32 reg_value; in sunxi_de2_composer_init() local
39 reg_value = readl(SUNXI_SRAMC_BASE + 0x04); in sunxi_de2_composer_init()
40 reg_value &= ~(0x01 << 24); in sunxi_de2_composer_init()
41 writel(reg_value, SUNXI_SRAMC_BASE + 0x04); in sunxi_de2_composer_init()
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| /rk3399_rockchip-uboot/include/ |
| H A D | cortina.h | 73 unsigned short reg_value; member
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| /rk3399_rockchip-uboot/drivers/power/regulator/ |
| H A D | rk8xx.c | 548 int reg_value, ramp_reg1, ramp_reg2; in _buck_set_ramp_delay() local
613 reg_value = pmic_reg_read(pmic, ramp_reg1); in _buck_set_ramp_delay()
614 if (reg_value < 0) { in _buck_set_ramp_delay()
615 printf("buck%d read ramp reg(0x%x) error: %d", buck, ramp_reg1, reg_value); in _buck_set_ramp_delay()
616 return reg_value; in _buck_set_ramp_delay()
618 reg_value &= 0x3f; in _buck_set_ramp_delay()
622 reg_value | (ramp_value & 0x03) << 0x06); in _buck_set_ramp_delay()
624 reg_value = pmic_reg_read(pmic, ramp_reg2); in _buck_set_ramp_delay()
625 if (reg_value < 0) { in _buck_set_ramp_delay()
626 printf("buck%d read ramp reg(0x%x) error: %d", buck, ramp_reg2, reg_value); in _buck_set_ramp_delay()
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| /rk3399_rockchip-uboot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_hw_training.h | 289 u32 reg_value; member
294 u32 reg_value; member
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| H A D | ddr3_init.c | 793 ddr_mode->vals[j].reg_value); in ddr3_static_training_init()
891 ddr_mode->regs[j].reg_value); in ddr3_static_mc_init()
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