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Searched refs:pll_con (Results 1 – 1 of 1) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3399.c342 static uint32_t rkclk_pll_get_rate(u32 *pll_con) in rkclk_pll_get_rate() argument
347 con = readl(&pll_con[3]); in rkclk_pll_get_rate()
353 con = readl(&pll_con[0]); in rkclk_pll_get_rate()
355 con = readl(&pll_con[1]); in rkclk_pll_get_rate()
366 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) in rkclk_set_pll() argument
374 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
384 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, in rkclk_set_pll()
388 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, in rkclk_set_pll()
391 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, in rkclk_set_pll()
393 rk_clrsetreg(&pll_con[1], in rkclk_set_pll()
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