Home
last modified time | relevance | path

Searched refs:phy_ctrl (Results 1 – 18 of 18) sorted by relevance

/rk3399_rockchip-uboot/drivers/usb/host/
H A Dehci-mx6.c151 void __iomem *phy_ctrl; in usb_phy_enable() local
159 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); in usb_phy_enable()
174 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); in usb_phy_enable()
178 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); in usb_phy_enable()
184 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | in usb_phy_enable()
193 void __iomem *phy_ctrl; in usb_phy_mode() local
197 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); in usb_phy_mode()
199 val = readl(phy_ctrl); in usb_phy_mode()
468 void *__iomem phy_ctrl, *__iomem phy_status; in ehci_usb_phy_mode() local
489 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL); in ehci_usb_phy_mode()
[all …]
H A Dehci-vf.c88 void __iomem *phy_ctrl; in usb_phy_enable() local
92 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); in usb_phy_enable()
105 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); in usb_phy_enable()
109 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); in usb_phy_enable()
116 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | in usb_phy_enable()
/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Ddmc_init_ddr3.c282 *phy_ctrl) in dmc_get_read_offset_value()
284 return readl(&phy_ctrl->phy_con4); in dmc_get_read_offset_value()
292 static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl) in ddr_phy_set_do_resync() argument
294 setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); in ddr_phy_set_do_resync()
295 clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); in ddr_phy_set_do_resync()
306 static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl, in dmc_set_read_offset_value() argument
309 writel(offset, &phy_ctrl->phy_con4); in dmc_set_read_offset_value()
310 ddr_phy_set_do_resync(phy_ctrl); in dmc_set_read_offset_value()
352 void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch, in test_shifts() argument
361 dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4); in test_shifts()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-aspeed/ast2500/
H A Dsdram_ast2500.c98 writel(0, &regs->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
101 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
102 while ((readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT)) in ast2500_ddr_phy_init_process()
105 &regs->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
110 writel(0, &info->regs->phy_ctrl[0]); in ast2500_sdrammc_set_vref()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-aspeed/
H A Dsdram_ast2500.h121 u32 phy_ctrl[4]; member
/rk3399_rockchip-uboot/drivers/net/
H A De1000.c2199 uint32_t phy_ctrl = 0; in e1000_set_d3_lplu_state() local
2221 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); in e1000_set_d3_lplu_state()
2239 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; in e1000_set_d3_lplu_state()
2240 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state()
2291 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; in e1000_set_d3_lplu_state()
2292 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state()
2334 uint32_t phy_ctrl = 0; in e1000_set_d0_lplu_state() local
2343 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); in e1000_set_d0_lplu_state()
2345 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); in e1000_set_d0_lplu_state()
2355 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; in e1000_set_d0_lplu_state()
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dsun8i-a23.dtsi105 reg-names = "phy_ctrl",
H A Dsun8i-a33.dtsi147 reg-names = "phy_ctrl",
H A Dsun8i-v3s.dtsi173 reg-names = "phy_ctrl",
H A Dsun50i-a64.dtsi192 reg-names = "phy_ctrl",
H A Dsun8i-h3.dtsi228 reg-names = "phy_ctrl",
H A Dsun5i.dtsi498 reg-names = "phy_ctrl", "pmu1";
H A Dam33xx.dtsi500 reg-names = "phy_ctrl", "wakeup";
H A Dsun5i-gr8.dtsi707 reg-names = "phy_ctrl", "pmu1";
H A Dsun6i-a31.dtsi569 reg-names = "phy_ctrl",
H A Dsun4i-a10.dtsi867 reg-names = "phy_ctrl", "pmu1", "pmu2";
H A Dsun7i-a20.dtsi996 reg-names = "phy_ctrl", "pmu1", "pmu2";
/rk3399_rockchip-uboot/arch/arm/mach-exynos/include/mach/
H A Ddp.h193 unsigned int phy_ctrl; member