Searched refs:mdiv (Results 1 – 7 of 7) sorted by relevance
| /rk3399_rockchip-uboot/drivers/clk/exynos/ |
| H A D | clk-pll.c | 23 unsigned long mdiv, sdiv, pdiv; in pll145x_get_rate() local
26 mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK; in pll145x_get_rate()
30 fvco *= mdiv; in pll145x_get_rate()
|
| /rk3399_rockchip-uboot/arch/arm/mach-exynos/ |
| H A D | exynos4_setup.h | 341 #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ argument
342 | (mdiv << 16) \
|
| H A D | exynos5_setup.h | 23 #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) argument
|
| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | phy-rockchip-samsung-hdptx-hdmi.c | 954 u32 mdiv, sdiv, n = 8; in hdptx_phy_clk_pll_calc() local
966 mdiv = DIV_ROUND_UP(fvco, fref); in hdptx_phy_clk_pll_calc()
967 if (mdiv < 20 || mdiv > 255) in hdptx_phy_clk_pll_calc()
970 if (fref * mdiv - fvco) { in hdptx_phy_clk_pll_calc()
972 if (sdc * n > fref * mdiv) in hdptx_phy_clk_pll_calc()
978 rational_best_approximation(fref * mdiv - fvco, in hdptx_phy_clk_pll_calc()
984 rational_best_approximation(sdc * n - fref * mdiv, in hdptx_phy_clk_pll_calc()
998 cfg->pms_mdiv = mdiv; in hdptx_phy_clk_pll_calc()
999 cfg->pms_mdiv_afc = mdiv; in hdptx_phy_clk_pll_calc()
|
| /rk3399_rockchip-uboot/board/samsung/trats/ |
| H A D | setup.h | 230 #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ argument
231 | (mdiv << 16) \
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra/ |
| H A D | bpmp_abi.h | 1368 uint16_t mdiv; /**< input divider value */ member
|
| /rk3399_rockchip-uboot/drivers/phy/ |
| H A D | phy-rockchip-samsung-hdptx.c | 366 u8 mdiv; member
930 FIELD_PREP(ROPLL_PMS_MDIV, pll_ctrl->mdiv)); in rockchip_hdptx_phy_set_rate()
|