Searched refs:mckr (Results 1 – 9 of 9) sorted by relevance
116 unsigned freq, mckr; in at91_clock_init() local156 mckr = readl(&pmc->mckr); in at91_clock_init()160 gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); in at91_clock_init()162 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); in at91_clock_init()167 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 4)); in at91_clock_init()169 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ in at91_clock_init()174 gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? in at91_clock_init()175 freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; in at91_clock_init()176 if (mckr & AT91_PMC_MCKR_MDIV_MASK) in at91_clock_init()186 gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == in at91_clock_init()[all …]
58 unsigned freq, mckr; in at91_clock_init() local85 mckr = readl(&pmc->mckr); in at91_clock_init()88 if (mckr & (1 << 12)) in at91_clock_init()91 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); in at91_clock_init()95 freq >>= mckr & AT91_PMC_MCKR_PRES_MASK; in at91_clock_init()97 switch (mckr & AT91_PMC_MCKR_MDIV_MASK) { in at91_clock_init()125 void at91_mck_init(u32 mckr) in at91_mck_init() argument130 tmp = readl(&pmc->mckr); in at91_mck_init()139 tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK | in at91_mck_init()144 tmp |= mckr & AT91_PMC_MCKR_H32MXDIV; in at91_mck_init()[all …]
108 unsigned freq, mckr; in at91_clock_init() local148 mckr = readl(&pmc->mckr); in at91_clock_init()149 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); in at91_clock_init()152 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ in at91_clock_init()155 (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); in at91_clock_init()
45 if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) { in lowlevel_clock_init()48 tmp = readl(&pmc->mckr); in lowlevel_clock_init()51 writel(tmp, &pmc->mckr); in lowlevel_clock_init()57 writel(tmp, &pmc->mckr); in lowlevel_clock_init()
27 void at91_mck_init(u32 mckr);32 void at91_mck_init(u32 mckr);
66 return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV; in get_h32mxdiv()
42 u32 mckr; /* 0x30 Master Clock Register */ member
26 if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV) in sama5d4_h32mx_clk_get_rate()
236 writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) | in misc_init_r()237 AT91SAM9_PMC_MDIV_4, &pmc->mckr); in misc_init_r()