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Searched refs:lw (Results 1 – 10 of 10) sorted by relevance

/rk3399_rockchip-uboot/arch/mips/mach-ath79/ar933x/
H A Dlowlevel_init.S83 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
87 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
101 lw t5, AR933X_RESET_REG_BOOTSTRAP(t0)
130 lw t1, AR933X_RTC_REG_STATUS(t0)
149 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
190 lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
216 lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
235 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
255 lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0)
260 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
/rk3399_rockchip-uboot/board/imgtec/boston/
H A Dlowlevel_init.S30 1: lw t1, 0(t0)
49 lw k1, 0(a0)
51 lw k1, 4(a0)
/rk3399_rockchip-uboot/arch/mips/mach-ath79/qca953x/
H A Dlowlevel_init.S103 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
108 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
123 lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
136 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
153 lw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
159 lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
165 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
/rk3399_rockchip-uboot/drivers/video/
H A Dbus_vcxk.c366 unsigned long lw; in vcxk_display_bitmap() local
391 lw = (((width + 7) / 8) + 3) & ~0x3; in vcxk_display_bitmap()
394 dataptr = dataptr + lw * (height - c_height); in vcxk_display_bitmap()
397 vcxk_draw_mono(dataptr, lw, c_width, c_height); in vcxk_display_bitmap()
/rk3399_rockchip-uboot/arch/mips/include/asm/
H A Dasm.h253 #define REG_L lw
274 #define INT_L lw
311 #define LONG_L lw
360 #define PTR_L lw
/rk3399_rockchip-uboot/board/imgtec/malta/
H A Dlowlevel_init.S33 lw t0, 0(t0)
111 lw t1, MSC01_PBC_CS0CFG_OFS(t0)
224 lw t1, MSC01_PCI_CFG_OFS(t0)
/rk3399_rockchip-uboot/arch/mips/lib/
H A Dcache_init.S153 lw t1, GCR_L2_CONFIG(t0)
369 lw t1, GCR_L2_CONFIG(t0)
411 lw t1, GCR_REV(t0)
/rk3399_rockchip-uboot/board/pb1x00/
H A Dlowlevel_init.S41 lw t2, 0(t1)
47 lw t2, 0(t1)
/rk3399_rockchip-uboot/arch/microblaze/cpu/
H A Dstart.S242 1: lw r12, r21, r5 /* Load u-boot data */
297 3: lw r12, r21, r0 /* Load entry */
/rk3399_rockchip-uboot/board/dbau1x00/
H A Dlowlevel_init.S53 lw t1,8(t0)