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Searched refs:link_bw (Results 1 – 6 of 6) sorted by relevance

/rk3399_rockchip-uboot/board/gdsys/common/
H A Ddp501.c53 u8 link_bw; in dp501_link_training() local
59 link_bw = 0x0a; in dp501_link_training()
61 link_bw = 0x06; in dp501_link_training()
62 if (link_bw != val) in dp501_link_training()
64 val * 270, link_bw * 270); in dp501_link_training()
65 i2c_reg_write(addr, 0x5d, link_bw); /* set link_bw */ in dp501_link_training()
/rk3399_rockchip-uboot/drivers/video/tegra124/
H A Ddp.c432 link_cfg->link_bw); in tegra_dc_dp_dump_link_cfg()
455 switch (cfg->link_bw) { in _tegra_dp_lower_link_config()
458 cfg->link_bw = SOR_LINK_SPEED_G2_7; in _tegra_dp_lower_link_config()
462 cfg->link_bw = SOR_LINK_SPEED_G1_62; in _tegra_dp_lower_link_config()
466 cfg->link_bw = SOR_LINK_SPEED_G2_7; in _tegra_dp_lower_link_config()
473 debug("dp: Error link rate %d\n", cfg->link_bw); in _tegra_dp_lower_link_config()
488 const u32 link_rate = 27 * link_cfg->link_bw * 1000 * 1000; in tegra_dc_dp_calc_config()
711 link_cfg->link_bw = link_cfg->max_link_bw; in tegra_dc_dp_init_max_link_cfg()
740 u8 link_bw) in tegra_dp_set_link_bandwidth() argument
742 tegra_dc_sor_set_link_bandwidth(sor, link_bw); in tegra_dp_set_link_bandwidth()
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H A Dsor.c170 reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ? in tegra_dc_sor_set_dp_linkctl()
282 tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw); in tegra_dc_sor_set_dp_mode()
389 void tegra_dc_sor_read_link_config(struct udevice *dev, u8 *link_bw, in tegra_dc_sor_read_link_config() argument
396 *link_bw = (reg_val & CLK_CNTRL_DP_LINK_SPEED_MASK) in tegra_dc_sor_read_link_config()
419 void tegra_dc_sor_set_link_bandwidth(struct udevice *dev, u8 link_bw) in tegra_dc_sor_set_link_bandwidth() argument
425 link_bw << CLK_CNTRL_DP_LINK_SPEED_SHIFT); in tegra_dc_sor_set_link_bandwidth()
845 tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw); in tegra_dc_sor_set_lane_parm()
869 switch (link_cfg->link_bw) { in tegra_dc_sor_set_voltage_swing()
878 debug("Invalid sor link bandwidth: %d\n", link_cfg->link_bw); in tegra_dc_sor_set_voltage_swing()
H A Dsor.h854 u8 link_bw; member
884 void tegra_dc_sor_set_link_bandwidth(struct udevice *dev, u8 link_bw);
889 void tegra_dc_sor_read_link_config(struct udevice *dev, u8 *link_bw,
/rk3399_rockchip-uboot/drivers/video/drm/
H A Ddrm_dp_helper.c143 int drm_dp_bw_code_to_link_rate(u8 link_bw) in drm_dp_bw_code_to_link_rate() argument
146 return link_bw * 27000; in drm_dp_bw_code_to_link_rate()
/rk3399_rockchip-uboot/include/drm/
H A Ddrm_dp_helper.h1023 int drm_dp_bw_code_to_link_rate(u8 link_bw);