Searched refs:fine (Results 1 – 16 of 16) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/mach-exynos/ |
| H A D | clock.c | 1445 unsigned int fine; in exynos5_set_spi_clk() local 1450 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine); in exynos5_set_spi_clk() 1457 fine = fine - 1; in exynos5_set_spi_clk() 1491 clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift); in exynos5_set_spi_clk() 1502 unsigned int fine; in exynos5420_set_spi_clk() local 1508 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine); in exynos5420_set_spi_clk() 1515 fine = fine - 1; in exynos5420_set_spi_clk() 1556 (fine & pre_div_mask) << pre_shift); in exynos5420_set_spi_clk()
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/net/ |
| H A D | stmmac.txt | 44 If not passed then the system clock will be used and this is fine on some
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| /rk3399_rockchip-uboot/doc/ |
| H A D | README.clang | 21 fine, but llvm might hardcode addresses in movw / movt pairs, which
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| H A D | README.multi-dtb-fit | 22 on the SOC than on the board. So it's usually fine to include a DTB in the
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| H A D | README.iomux | 79 characters) lines works fine when serial is the only device used.
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| H A D | README.socfpga | 23 This text is assuming quartus 16.1, but newer versions will probably work just fine too;
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| H A D | README.drivers.eth | 102 need to pass more/less arguments, that's fine. You should also add the
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| H A D | README.unaligned-memory-access.txt | 18 For example, reading 4 bytes of data from address 0x10004 is fine, but
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| /rk3399_rockchip-uboot/board/ccv/xpress/ |
| H A D | imximage.cfg | 101 * For target board, may need to run write leveling calibration to fine tune
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| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | exynos5420-peach-pit.dts | 99 * measure for fine tune b00: 1us,
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| H A D | exynos5250-spring.dts | 550 * measure for fine tune b00: 1us,
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| /rk3399_rockchip-uboot/drivers/usb/host/ |
| H A D | Kconfig | 247 that size it is possible to shrink it. Smaller sizes should be fine
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| /rk3399_rockchip-uboot/board/freescale/mx6qarm2/ |
| H A D | imximage_mx6dl.cfg | 315 * May need to run calibration on target board to fine tune these
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| /rk3399_rockchip-uboot/drivers/net/ |
| H A D | e1000.c | 4522 uint16_t fused, fine, coarse; in e1000_phy_init_script() local 4532 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; in e1000_phy_init_script() 4540 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; in e1000_phy_init_script() 4543 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; in e1000_phy_init_script() 4547 (fine in e1000_phy_init_script()
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| /rk3399_rockchip-uboot/cmd/ |
| H A D | Kconfig | 1242 This is most useful when fine-tuning the operation of the cache
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| /rk3399_rockchip-uboot/ |
| H A D | README | 1609 You can fine tune the DHCP functionality by defining 4881 option should work for you. Using CS 4 should be fine if your
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