1 /*
2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #ifndef _ROCKCHIP_VOP_H_
8 #define _ROCKCHIP_VOP_H_
9 #include "rockchip_display.h"
10 #include <asm/gpio.h>
11
12
13 #define VOP_REG_SUPPORT(vop, reg) \
14 (reg.mask && \
15 (!reg.major || \
16 (reg.major == VOP_MAJOR(vop->version) && \
17 reg.begin_minor <= VOP_MINOR(vop->version) && \
18 reg.end_minor >= VOP_MINOR(vop->version))))
19
20 #define VOP_WIN_SUPPORT(vop, win, name) \
21 VOP_REG_SUPPORT(vop, win->name)
22
23 #define VOP_CTRL_SUPPORT(vop, name) \
24 VOP_REG_SUPPORT(vop, vop->ctrl->name)
25
26 #define __REG_SET(x, off, mask, shift, v, write_mask) \
27 vop_mask_write(x, off, mask, shift, v, write_mask)
28
29 #define _REG_SET(vop, name, off, reg, mask, v) \
30 do { \
31 if (VOP_REG_SUPPORT(vop, reg)) \
32 __REG_SET(vop, off + reg.offset, mask, reg.shift, \
33 v, reg.write_mask); \
34 else \
35 debug("Warning: not support "#name"\n"); \
36 } while(0)
37
38 #define REG_SET(x, name, off, reg, v) \
39 _REG_SET(x, name, off, reg, reg.mask, v)
40 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
41 _REG_SET(x, name, off, reg, reg.mask & mask, v)
42
43 #define VOP_WIN_SET(x, name, v) \
44 REG_SET(x, name, x->win_offset, x->win->name, v)
45 #define VOP_WIN_SET_EXT(x, ext, name, v) \
46 REG_SET(x, name, x->win_offset, x->win->ext->name, v)
47 #define VOP_SCL_SET(x, name, v) \
48 REG_SET(x, name, x->win_offset, x->win->scl->name, v)
49 #define VOP_SCL_SET_EXT(x, name, v) \
50 REG_SET(x, name, x->win_offset, x->win->scl->ext->name, v)
51
52 #define VOP_CTRL_SET(x, name, v) \
53 REG_SET(x, name, 0, (x)->ctrl->name, v)
54 #define VOP_LINE_FLAG_SET(x, name, v) \
55 REG_SET(x, name, 0, (x)->line_flag->name, v)
56 #define VOP_WIN_CSC_SET(x, name, v) \
57 REG_SET(x, name, 0, (x)->win_csc->name, v)
58
59 #define VOP_CTRL_GET(x, name) \
60 vop_read_reg(x, 0, &vop->ctrl->name)
61
62 #define VOP_WIN_GET(x, name) \
63 vop_read_reg(x, vop->win->offset, &vop->win->name)
64
65 #define VOP_GRF_SET(vop, grf, reg, v) \
66 do { \
67 if (vop->data->grf) { \
68 vop_grf_writel(vop->grf, vop->data->grf->reg, v); \
69 } \
70 } while (0)
71
72 #define CVBS_PAL_VDISPLAY 288
73
74 enum alpha_mode {
75 ALPHA_STRAIGHT,
76 ALPHA_INVERSE,
77 };
78
79 enum global_blend_mode {
80 ALPHA_GLOBAL,
81 ALPHA_PER_PIX,
82 ALPHA_PER_PIX_GLOBAL,
83 };
84
85 enum alpha_cal_mode {
86 ALPHA_SATURATION,
87 ALPHA_NO_SATURATION,
88 };
89
90 enum color_mode {
91 ALPHA_SRC_PRE_MUL,
92 ALPHA_SRC_NO_PRE_MUL,
93 };
94
95 enum factor_mode {
96 ALPHA_ZERO,
97 ALPHA_ONE,
98 ALPHA_SRC,
99 ALPHA_SRC_INVERSE,
100 ALPHA_SRC_GLOBAL,
101 };
102
103 enum scale_mode {
104 SCALE_NONE = 0x0,
105 SCALE_UP = 0x1,
106 SCALE_DOWN = 0x2
107 };
108
109 enum lb_mode {
110 LB_YUV_3840X5 = 0x0,
111 LB_YUV_2560X8 = 0x1,
112 LB_RGB_3840X2 = 0x2,
113 LB_RGB_2560X4 = 0x3,
114 LB_RGB_1920X5 = 0x4,
115 LB_RGB_1280X8 = 0x5
116 };
117
118 enum sacle_up_mode {
119 SCALE_UP_BIL = 0x0,
120 SCALE_UP_BIC = 0x1
121 };
122
123 enum scale_down_mode {
124 SCALE_DOWN_BIL = 0x0,
125 SCALE_DOWN_AVG = 0x1
126 };
127
128 enum dither_down_mode {
129 RGB888_TO_RGB565 = 0x0,
130 RGB888_TO_RGB666 = 0x1
131 };
132
133 enum dither_down_mode_sel {
134 DITHER_DOWN_ALLEGRO = 0x0,
135 DITHER_DOWN_FRC = 0x1
136 };
137
138 enum vop_csc_format {
139 CSC_BT601L,
140 CSC_BT709L,
141 CSC_BT601F,
142 CSC_BT2020L,
143 CSC_BT709L_13BIT,
144 CSC_BT709F_13BIT,
145 CSC_BT2020L_13BIT,
146 CSC_BT2020F_13BIT,
147 };
148
149 enum vop_pol {
150 HSYNC_POSITIVE = 0,
151 VSYNC_POSITIVE = 1,
152 DEN_NEGATIVE = 2,
153 DCLK_INVERT = 3
154 };
155
156 #define DSP_BG_SWAP 0x1
157 #define DSP_RB_SWAP 0x2
158 #define DSP_RG_SWAP 0x4
159 #define DSP_DELTA_SWAP 0x8
160
161 #define PRE_DITHER_DOWN_EN(x) ((x) << 0)
162 #define DITHER_DOWN_EN(x) ((x) << 1)
163 #define DITHER_DOWN_MODE(x) ((x) << 2)
164 #define DITHER_DOWN_MODE_SEL(x) ((x) << 3)
165
166 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
167 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
168 #define SCL_MAX_VSKIPLINES 4
169 #define MIN_SCL_FT_AFTER_VSKIP 1
170
171 #define VOP_PLANE_NO_SCALING BIT(16)
172
scl_cal_scale(int src,int dst,int shift)173 static inline uint16_t scl_cal_scale(int src, int dst, int shift)
174 {
175 return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
176 }
177
scl_cal_scale2(int src,int dst)178 static inline uint16_t scl_cal_scale2(int src, int dst)
179 {
180 return ((src - 1) << 12) / (dst - 1);
181 }
182
183 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
184 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
185 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
186
scl_get_bili_dn_vskip(int src_h,int dst_h,int vskiplines)187 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
188 int vskiplines)
189 {
190 int act_height;
191
192 act_height = (src_h + vskiplines - 1) / vskiplines;
193
194 return GET_SCL_FT_BILI_DN(act_height, dst_h);
195 }
196
scl_get_scl_mode(int src,int dst)197 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
198 {
199 if (src < dst)
200 return SCALE_UP;
201 else if (src > dst)
202 return SCALE_DOWN;
203
204 return SCALE_NONE;
205 }
206
scl_get_vskiplines(uint32_t srch,uint32_t dsth)207 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
208 {
209 uint32_t vskiplines;
210
211 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
212 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
213 break;
214
215 return vskiplines;
216 }
217
scl_vop_cal_lb_mode(int width,bool is_yuv)218 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
219 {
220 int lb_mode;
221
222 if (width > 2560)
223 lb_mode = LB_RGB_3840X2;
224 else if (width > 1920)
225 lb_mode = LB_RGB_2560X4;
226 else if (!is_yuv)
227 lb_mode = LB_RGB_1920X5;
228 else if (width > 1280)
229 lb_mode = LB_YUV_3840X5;
230 else
231 lb_mode = LB_YUV_2560X8;
232
233 return lb_mode;
234 }
235
236 struct vop_reg_data {
237 uint32_t offset;
238 uint32_t value;
239 };
240
241 struct vop_reg {
242 uint32_t mask;
243 uint32_t offset:19;
244 uint32_t shift:5;
245 uint32_t begin_minor:4;
246 uint32_t end_minor:4;
247 uint32_t major:3;
248 uint32_t write_mask:1;
249 };
250
251 struct vop_ctrl {
252 struct vop_reg standby;
253 struct vop_reg axi_outstanding_max_num;
254 struct vop_reg axi_max_outstanding_en;
255 struct vop_reg htotal_pw;
256 struct vop_reg hact_st_end;
257 struct vop_reg vtotal_pw;
258 struct vop_reg vact_st_end;
259 struct vop_reg vact_st_end_f1;
260 struct vop_reg vs_st_end_f1;
261 struct vop_reg hpost_st_end;
262 struct vop_reg vpost_st_end;
263 struct vop_reg vpost_st_end_f1;
264 struct vop_reg post_scl_factor;
265 struct vop_reg post_scl_ctrl;
266 struct vop_reg dsp_interlace;
267 struct vop_reg dsp_interlace_pol;
268 struct vop_reg global_regdone_en;
269 struct vop_reg auto_gate_en;
270 struct vop_reg post_lb_mode;
271 struct vop_reg dsp_layer_sel;
272 struct vop_reg overlay_mode;
273 struct vop_reg core_dclk_div;
274 struct vop_reg dclk_ddr;
275 struct vop_reg p2i_en;
276 struct vop_reg hdmi_dclk_out_en;
277 struct vop_reg rgb_en;
278 struct vop_reg lvds_en;
279 struct vop_reg edp_en;
280 struct vop_reg hdmi_en;
281 struct vop_reg mipi_en;
282 struct vop_reg data01_swap;
283 struct vop_reg mipi_dual_channel_en;
284 struct vop_reg dp_en;
285 struct vop_reg dclk_pol;
286 struct vop_reg pin_pol;
287 struct vop_reg rgb_dclk_pol;
288 struct vop_reg rgb_pin_pol;
289 struct vop_reg lvds_dclk_pol;
290 struct vop_reg lvds_pin_pol;
291 struct vop_reg hdmi_dclk_pol;
292 struct vop_reg hdmi_pin_pol;
293 struct vop_reg edp_dclk_pol;
294 struct vop_reg edp_pin_pol;
295 struct vop_reg mipi_dclk_pol;
296 struct vop_reg mipi_pin_pol;
297 struct vop_reg dp_dclk_pol;
298 struct vop_reg dp_pin_pol;
299
300 struct vop_reg dither_up;
301 struct vop_reg dither_down;
302
303 struct vop_reg sw_dac_sel;
304 struct vop_reg tve_sw_mode;
305 struct vop_reg tve_dclk_pol;
306 struct vop_reg tve_dclk_en;
307 struct vop_reg sw_genlock;
308 struct vop_reg sw_uv_offset_en;
309
310 struct vop_reg dsp_out_yuv;
311 struct vop_reg dsp_data_swap;
312 struct vop_reg dsp_bg_swap;
313 struct vop_reg dsp_rb_swap;
314 struct vop_reg dsp_rg_swap;
315 struct vop_reg dsp_delta_swap;
316 struct vop_reg dsp_dummy_swap;
317 struct vop_reg yuv_clip;
318 struct vop_reg dsp_ccir656_avg;
319 struct vop_reg dsp_black;
320 struct vop_reg dsp_blank;
321 struct vop_reg dsp_outzero;
322 struct vop_reg dsp_lut_en;
323 struct vop_reg update_gamma_lut;
324
325 struct vop_reg out_mode;
326
327 struct vop_reg xmirror;
328 struct vop_reg ymirror;
329 struct vop_reg dsp_background;
330
331 /* CABC */
332 struct vop_reg cabc_total_num;
333 struct vop_reg cabc_config_mode;
334 struct vop_reg cabc_stage_up_mode;
335 struct vop_reg cabc_scale_cfg_value;
336 struct vop_reg cabc_scale_cfg_enable;
337 struct vop_reg cabc_global_dn_limit_en;
338 struct vop_reg cabc_lut_en;
339 struct vop_reg cabc_en;
340 struct vop_reg cabc_handle_en;
341 struct vop_reg cabc_stage_up;
342 struct vop_reg cabc_stage_down;
343 struct vop_reg cabc_global_dn;
344 struct vop_reg cabc_calc_pixel_num;
345
346 struct vop_reg win_gate[4];
347 struct vop_reg win_channel[4];
348
349 /* BCSH */
350 struct vop_reg bcsh_brightness;
351 struct vop_reg bcsh_contrast;
352 struct vop_reg bcsh_sat_con;
353 struct vop_reg bcsh_sin_hue;
354 struct vop_reg bcsh_cos_hue;
355 struct vop_reg bcsh_r2y_csc_mode;
356 struct vop_reg bcsh_r2y_en;
357 struct vop_reg bcsh_y2r_csc_mode;
358 struct vop_reg bcsh_y2r_en;
359 struct vop_reg bcsh_color_bar;
360 struct vop_reg bcsh_out_mode;
361 struct vop_reg bcsh_en;
362 struct vop_reg reg_done_frm;
363
364 /* MCU OUTPUT */
365 struct vop_reg mcu_pix_total;
366 struct vop_reg mcu_cs_pst;
367 struct vop_reg mcu_cs_pend;
368 struct vop_reg mcu_rw_pst;
369 struct vop_reg mcu_rw_pend;
370 struct vop_reg mcu_clk_sel;
371 struct vop_reg mcu_hold_mode;
372 struct vop_reg mcu_frame_st;
373 struct vop_reg mcu_rs;
374 struct vop_reg mcu_bypass;
375 struct vop_reg mcu_type;
376 struct vop_reg mcu_rw_bypass_port;
377 struct vop_reg mcu_force_rdn;
378
379 /* bt1120 */
380 struct vop_reg bt1120_uv_swap;
381 struct vop_reg bt1120_yc_swap;
382 struct vop_reg bt1120_en;
383
384 /* bt656 */
385 struct vop_reg bt656_en;
386
387 struct vop_reg cfg_done;
388
389 /* ebc vop */
390 struct vop_reg enable;
391 struct vop_reg inf_out_en;
392 struct vop_reg out_dresetn;
393 };
394
395 struct vop_scl_extension {
396 struct vop_reg cbcr_vsd_mode;
397 struct vop_reg cbcr_vsu_mode;
398 struct vop_reg cbcr_hsd_mode;
399 struct vop_reg cbcr_ver_scl_mode;
400 struct vop_reg cbcr_hor_scl_mode;
401 struct vop_reg yrgb_vsd_mode;
402 struct vop_reg yrgb_vsu_mode;
403 struct vop_reg yrgb_hsd_mode;
404 struct vop_reg yrgb_ver_scl_mode;
405 struct vop_reg yrgb_hor_scl_mode;
406 struct vop_reg line_load_mode;
407 struct vop_reg cbcr_axi_gather_num;
408 struct vop_reg yrgb_axi_gather_num;
409 struct vop_reg vsd_cbcr_gt2;
410 struct vop_reg vsd_cbcr_gt4;
411 struct vop_reg vsd_yrgb_gt2;
412 struct vop_reg vsd_yrgb_gt4;
413 struct vop_reg bic_coe_sel;
414 struct vop_reg cbcr_axi_gather_en;
415 struct vop_reg yrgb_axi_gather_en;
416 struct vop_reg lb_mode;
417 };
418
419 struct vop_scl_regs {
420 const struct vop_scl_extension *ext;
421
422 struct vop_reg scale_yrgb_x;
423 struct vop_reg scale_yrgb_y;
424 struct vop_reg scale_cbcr_x;
425 struct vop_reg scale_cbcr_y;
426 };
427
428 struct vop_win {
429 const struct vop_scl_regs *scl;
430
431 struct vop_reg gate;
432 struct vop_reg enable;
433 struct vop_reg format;
434 struct vop_reg interlace_read;
435 struct vop_reg ymirror;
436 struct vop_reg rb_swap;
437 struct vop_reg act_info;
438 struct vop_reg dsp_info;
439 struct vop_reg dsp_st;
440 struct vop_reg yrgb_mst;
441 struct vop_reg uv_mst;
442 struct vop_reg yrgb_vir;
443 struct vop_reg uv_vir;
444 struct vop_reg alpha_mode;
445 struct vop_reg alpha_en;
446
447 struct vop_reg dst_alpha_ctl;
448 struct vop_reg src_alpha_ctl;
449 };
450
451 struct vop_line_flag {
452 struct vop_reg line_flag_num[2];
453 };
454
455 struct vop_grf_ctrl {
456 struct vop_reg grf_dclk_inv;
457 struct vop_reg grf_vopl_sel;
458 struct vop_reg grf_edp_ch_sel;
459 struct vop_reg grf_hdmi_ch_sel;
460 struct vop_reg grf_mipi_ch_sel;
461 struct vop_reg grf_hdmi_pin_pol;
462 struct vop_reg grf_hdmi_1to4_en;
463 struct vop_reg grf_mipi_mode;
464 struct vop_reg grf_mipi_pin_pol;
465 struct vop_reg grf_mipi_1to4_en;
466 };
467
468 struct vop_csc_table {
469 const uint32_t *r2y_bt601;
470 const uint32_t *r2y_bt601_12_235;
471 const uint32_t *r2y_bt709;
472 const uint32_t *r2y_bt2020;
473 };
474
475 struct vop_csc {
476 struct vop_reg y2r_en;
477 struct vop_reg r2r_en;
478 struct vop_reg r2y_en;
479
480 uint32_t y2r_offset;
481 uint32_t r2r_offset;
482 uint32_t r2y_offset;
483 };
484
485 #define VOP_FEATURE_OUTPUT_10BIT BIT(0)
486
487 struct vop_data {
488 uint32_t version;
489 const struct vop_ctrl *ctrl;
490 const struct vop_win *win;
491 const struct vop_line_flag *line_flag;
492 const struct vop_grf_ctrl *grf_ctrl;
493 const struct vop_grf_ctrl *vo0_grf_ctrl;
494 const struct vop_csc_table *csc_table;
495 const struct vop_csc *win_csc;
496 int win_offset;
497 int reg_len;
498 u64 feature;
499 struct vop_rect max_output;
500 };
501
502 struct vop {
503 u32 *regsbak;
504 void *regs;
505 void *grf_ctrl;
506 void *vo0_grf_ctrl;
507
508 uint32_t version;
509 const struct vop_ctrl *ctrl;
510 const struct vop_win *win;
511 const struct vop_line_flag *line_flag;
512 const struct vop_csc_table *csc_table;
513 const struct vop_csc *win_csc;
514 const struct vop_data *data;
515 int win_offset;
516
517 struct gpio_desc mcu_rs_gpio;
518 };
519
vop_writel(struct vop * vop,uint32_t offset,uint32_t v)520 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
521 {
522 writel(v, vop->regs + offset);
523 vop->regsbak[offset >> 2] = v;
524 }
525
vop_readl(struct vop * vop,uint32_t offset)526 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
527 {
528 return readl(vop->regs + offset);
529 }
530
vop_read_reg(struct vop * vop,uint32_t base,const struct vop_reg * reg)531 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
532 const struct vop_reg *reg)
533 {
534 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
535 }
536
vop_mask_write(struct vop * vop,uint32_t offset,uint32_t mask,uint32_t shift,uint32_t v,bool write_mask)537 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
538 uint32_t mask, uint32_t shift, uint32_t v,
539 bool write_mask)
540 {
541 if (!mask)
542 return;
543
544 if (write_mask) {
545 v = ((v & mask) << shift) | (mask << (shift + 16));
546 } else {
547 uint32_t cached_val = vop->regsbak[offset >> 2];
548
549 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
550 vop->regsbak[offset >> 2] = v;
551 }
552
553 writel(v, vop->regs + offset);
554 }
555
vop_cfg_done(struct vop * vop)556 static inline void vop_cfg_done(struct vop *vop)
557 {
558 VOP_CTRL_SET(vop, cfg_done, 1);
559 }
560
vop_grf_writel(void * regmap,struct vop_reg reg,u32 v)561 static inline void vop_grf_writel(void *regmap, struct vop_reg reg, u32 v)
562 {
563 u32 val = 0;
564
565 if (reg.mask) {
566 val = (v << reg.shift) | (reg.mask << (reg.shift + 16));
567 writel(val, regmap + reg.offset);
568 }
569 }
570
571 /**
572 * drm_format_horz_chroma_subsampling - get the horizontal chroma subsampling factor
573 * @format: pixel format (DRM_FORMAT_*)
574 *
575 * Returns:
576 * The horizontal chroma subsampling factor for the
577 * specified pixel format.
578 */
drm_format_horz_chroma_subsampling(uint32_t format)579 static inline int drm_format_horz_chroma_subsampling(uint32_t format)
580 {
581 /* uboot only support RGB format */
582 return 1;
583 }
584
585 /**
586 * drm_format_vert_chroma_subsampling - get the vertical chroma subsampling factor
587 * @format: pixel format (DRM_FORMAT_*)
588 *
589 * Returns:
590 * The vertical chroma subsampling factor for the
591 * specified pixel format.
592 */
drm_format_vert_chroma_subsampling(uint32_t format)593 static inline int drm_format_vert_chroma_subsampling(uint32_t format)
594 {
595 /* uboot only support RGB format */
596 return 1;
597 }
598
599 #endif
600