Searched refs:ep0state (Results 1 – 9 of 9) sorted by relevance
27 static int ep0state = EP0_IDLE; variable128 ep0state = EP0_IDLE; in udc_write_urb()130 ep0state = EP0_XFER_COMPLETE; in udc_write_urb()215 ep0state = EP0_IDLE; in udc_handle_ep0()219 if ((udccsr0 & UDCCSR0_SA) != 0 && ep0state != EP0_IDLE) in udc_handle_ep0()220 ep0state = EP0_IDLE; in udc_handle_ep0()222 switch (ep0state) { in udc_handle_ep0()259 ep0state = EP0_IDLE; in udc_handle_ep0()265 ep0state = EP0_OUT_DATA; in udc_handle_ep0()284 ep0state = EP0_IDLE; in udc_handle_ep0()[all …]
41 dev->ep0state = WAIT_FOR_IN_COMPLETE; in dwc2_udc_ep0_zlp()245 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) { in complete_rx()249 dev->ep0state = WAIT_FOR_IN_COMPLETE; in complete_rx()273 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) { in complete_tx()274 dev->ep0state = WAIT_FOR_OUT_COMPLETE; in complete_tx()302 if (dev->ep0state == DATA_STATE_XMIT) { in complete_tx()309 dev->ep0state = WAIT_FOR_COMPLETE; in complete_tx()310 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) { in complete_tx()315 dev->ep0state = WAIT_FOR_SETUP; in complete_tx()316 } else if (dev->ep0state == WAIT_FOR_COMPLETE) { in complete_tx()[all …]
103 if (dev->ep0state == EP0_STALL in udc_watchdog()143 label, state_name[the_controller->ep0state], udccs0, in dump_udccs0()161 state_name[dev->ep0state], in dump_state()441 dev->ep0state = EP0_IDLE; in ep0_idle()773 switch (dev->ep0state) { in pxa25x_ep_queue()791 dev->ep0state = EP0_END_XFER; in pxa25x_ep_queue()810 dev->ep0state); in pxa25x_ep_queue()926 ep->dev->ep0state = EP0_STALL; in pxa25x_ep_set_halt()1135 dev->ep0state = EP0_IDLE; in udc_reinit()1239 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) { in handle_ep0()[all …]
81 int ep0state; member
122 enum ep0_state ep0state; member
175 dev->ep0state = WAIT_FOR_SETUP; in udc_disable()195 dev->ep0state = WAIT_FOR_SETUP; in udc_reinit()
135 if (dwc->ep0state != EP0_DATA_PHASE) { in __dwc3_gadget_ep0_queue()159 if (dwc->ep0state == EP0_STATUS_PHASE) in __dwc3_gadget_ep0_queue()203 dwc->ep0state = EP0_DATA_PHASE; in __dwc3_gadget_ep0_queue()240 dwc3_ep0_state_string(dwc->ep0state)); in dwc3_gadget_ep0_queue()271 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_ep0_stall_and_restart()900 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_ep0_complete_status()913 switch (dwc->ep0state) { in dwc3_ep0_xfer_complete()929 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); in dwc3_ep0_xfer_complete()1079 dwc->ep0state = EP0_STATUS_PHASE; in dwc3_ep0_xfernotready()1099 dwc3_ep0_state_string(dwc->ep0state)); in dwc3_ep0_interrupt()
789 enum dwc3_ep0_state ep0state; member
1536 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_gadget_start()