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Searched refs:dq (Results 1 – 11 of 11) sorted by relevance

/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c97 u32 pup, dq, pups, cur_max_pup, valid_pup, reg; in ddr3_pbs_tx() local
126 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_tx()
127 skew_sum_array[pup][dq] = 0; in ddr3_pbs_tx()
174 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
177 (max_pup - 1)][dq] = in ddr3_pbs_tx()
201 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
207 [dq], CS0, (1 - ecc) * in ddr3_pbs_tx()
254 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
263 DEBUG_PBS_D(dq, 1); in ddr3_pbs_tx()
267 dq], 2); in ddr3_pbs_tx()
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H A Dddr3_dqs.c313 u32 dq; in ddr3_find_adll_limits() local
347 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_find_adll_limits()
348 analog_pbs_sum[pup][dq][0] = adll_start_val; in ddr3_find_adll_limits()
349 analog_pbs_sum[pup][dq][1] = adll_end_val; in ddr3_find_adll_limits()
379 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_find_adll_limits()
380 analog_pbs[victim_dq][pup][dq][0] = in ddr3_find_adll_limits()
382 analog_pbs[victim_dq][pup][dq][1] = in ddr3_find_adll_limits()
384 per_bit_data[pup][dq] = 0; in ddr3_find_adll_limits()
463 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_find_adll_limits()
464 if ((analog_pbs[victim_dq][pup][dq][0] != adll_start_val) in ddr3_find_adll_limits()
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H A Dddr3_sdram.c99 __maybe_unused u32 dq; in compare_pattern_v1() local
115 for (dq = 0; dq < DQ_NUM; dq++) { in compare_pattern_v1()
118 if (((var1 >> dq) & 0x1) != in compare_pattern_v1()
119 ((var2 >> dq) & 0x1)) in compare_pattern_v1()
120 per_bit_data[val][dq] = 1; in compare_pattern_v1()
122 per_bit_data[val][dq] = 0; in compare_pattern_v1()
172 __maybe_unused u32 dq; in ddr3_sdram_compare() local
292 u32 ui, dq, pup; in ddr3_sdram_pbs_compare() local
364 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_sdram_pbs_compare()
367 if (((var1 >> dq) & 0x1) != in ddr3_sdram_pbs_compare()
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H A Dddr3_hw_training.c698 u32 val, pup, tmp_cs, cs, i, dq; in ddr3_save_training() local
739 for (dq = 0; dq <= DQ_NUM; in ddr3_save_training()
740 dq++) { in ddr3_save_training()
742 mode_config[i] + dq, in ddr3_save_training()
/rk3399_rockchip-uboot/cmd/ddr_tool/ddr_dq_eye/
H A Dddr_dq_eye.c40 u8 dq; in calc_print_border() local
53 for (dq = 0; dq < 8; dq++) { in calc_print_border()
54 if (result->dqs[dqs].dq_min[dq] < far_left) in calc_print_border()
55 far_left = result->dqs[dqs].dq_min[dq]; in calc_print_border()
56 if (result->dqs[dqs].dq_max[dq] > far_right) in calc_print_border()
57 far_right = result->dqs[dqs].dq_max[dq]; in calc_print_border()
99 u8 dq; in print_ddr_dq_eye() local
107 for (dq = 0; dq < 8; dq++) { in print_ddr_dq_eye()
109 result->dqs[dqs].dq_deskew[dq]; in print_ddr_dq_eye()
110 min = result->dqs[dqs].dq_min[dq]; in print_ddr_dq_eye()
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/rk3399_rockchip-uboot/drivers/net/fsl-mc/dpio/
H A Dqbman_portal.c375 const struct ldpaa_dq *dq; in qbman_swp_dqrr_next() local
378 dq = qbman_cena_read(&s->sys, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); in qbman_swp_dqrr_next()
379 p = qb_cl(dq); in qbman_swp_dqrr_next()
405 flags = ldpaa_dq_flags(dq); in qbman_swp_dqrr_next()
414 return dq; in qbman_swp_dqrr_next()
418 void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct ldpaa_dq *dq) in qbman_swp_dqrr_consume() argument
420 qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq)); in qbman_swp_dqrr_consume()
427 void qbman_dq_entry_set_oldtoken(struct ldpaa_dq *dq, in qbman_dq_entry_set_oldtoken() argument
431 memset(dq, oldtoken, num_entries * sizeof(*dq)); in qbman_dq_entry_set_oldtoken()
435 const struct ldpaa_dq *dq, in qbman_dq_entry_has_newtoken() argument
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/rk3399_rockchip-uboot/include/fsl-mc/
H A Dfsl_dpaa_fd.h101 static inline int ldpaa_dq_is_pull(const struct ldpaa_dq *dq) in ldpaa_dq_is_pull() argument
103 return (int)(ldpaa_dq_flags(dq) & LDPAA_DQ_STAT_VOLATILE); in ldpaa_dq_is_pull()
106 const struct ldpaa_dq *dq) in ldpaa_dq_is_pull_complete() argument
108 return (int)(ldpaa_dq_flags(dq) & LDPAA_DQ_STAT_EXPIRED); in ldpaa_dq_is_pull_complete()
/rk3399_rockchip-uboot/cmd/ddr_tool/
H A DKconfig6 This enable ddr tool such as ddr dq eye, ddr test tool, memtester and stressapptest.
12 This enable ddr dq eye fuction.
/rk3399_rockchip-uboot/drivers/net/ldpaa_eth/
H A Dldpaa_eth.c258 const struct ldpaa_dq *dq; in ldpaa_eth_pull_dequeue_rx() local
280 dq = qbman_swp_dqrr_next(swp); in ldpaa_eth_pull_dequeue_rx()
281 } while (get_timer(time_start) < timeo && !dq); in ldpaa_eth_pull_dequeue_rx()
283 if (dq) { in ldpaa_eth_pull_dequeue_rx()
289 status = (uint8_t)ldpaa_dq_flags(dq); in ldpaa_eth_pull_dequeue_rx()
294 qbman_swp_dqrr_consume(swp, dq); in ldpaa_eth_pull_dequeue_rx()
298 fd = ldpaa_dq_fd(dq); in ldpaa_eth_pull_dequeue_rx()
302 qbman_swp_dqrr_consume(swp, dq); in ldpaa_eth_pull_dequeue_rx()
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rv1126.c2033 u8 dq; in save_rw_trn_min_max() local
2043 for (dq = 0; dq < 8; dq++) { in save_rw_trn_min_max()
2044 rd_result->dqs[dqs].dq_min[dq] = in save_rw_trn_min_max()
2045 readb(PHY_REG(phy_base, phy_ofs + 0x15 + dq)); in save_rw_trn_min_max()
2046 rd_result->dqs[dqs].dq_max[dq] = in save_rw_trn_min_max()
2047 readb(PHY_REG(phy_base, phy_ofs + 0x27 + dq)); in save_rw_trn_min_max()
2048 wr_result->dqs[dqs].dq_min[dq] = in save_rw_trn_min_max()
2049 readb(PHY_REG(phy_base, phy_ofs + 0x3d + dq)); in save_rw_trn_min_max()
2050 wr_result->dqs[dqs].dq_max[dq] = in save_rw_trn_min_max()
2051 readb(PHY_REG(phy_base, phy_ofs + 0x4f + dq)); in save_rw_trn_min_max()
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/rk3399_rockchip-uboot/drivers/ram/rockchip/sdram_inc/rv1126/
H A Dsdram-rv1126-loader_params.inc137 /* ddr4 dq map */