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Searched refs:dmc (Results 1 – 25 of 72) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Ddmc_init_exynos4.c51 static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc) in phy_control_reset() argument
55 &dmc->phycontrol1); in phy_control_reset()
57 &dmc->phycontrol1); in phy_control_reset()
60 &dmc->phycontrol0); in phy_control_reset()
62 &dmc->phycontrol0); in phy_control_reset()
66 static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip) in dmc_config_mrs() argument
76 &dmc->directcmd); in dmc_config_mrs()
80 static void dmc_init(struct exynos4_dmc *dmc) in dmc_init() argument
87 writel(mem.control1, &dmc->phycontrol1); in dmc_init()
94 writel(mem.zqcontrol, &dmc->phyzqcontrol); in dmc_init()
[all …]
H A Ddmc_init_ddr3.c40 struct exynos5_dmc *dmc; in ddr3_mem_ctrl_init() local
46 dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl(); in ddr3_mem_ctrl_init()
76 &dmc->concontrol); in ddr3_mem_ctrl_init()
78 update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
103 update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
106 &dmc->concontrol); in ddr3_mem_ctrl_init()
109 writel(mem->iv_size, &dmc->ivcontrol); in ddr3_mem_ctrl_init()
111 writel(mem->memconfig, &dmc->memconfig0); in ddr3_mem_ctrl_init()
112 writel(mem->memconfig, &dmc->memconfig1); in ddr3_mem_ctrl_init()
113 writel(mem->membaseconfig0, &dmc->membaseconfig0); in ddr3_mem_ctrl_init()
[all …]
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Drockchip,rk3368-dmc.txt15 - compatible: "rockchip,rk3368-dmc"
54 #include <dt-bindings/memory/rk3368-dmc.h>
56 dmc: dmc@ff610000 {
58 compatible = "rockchip,rk3368-dmc";
63 &dmc {
H A Drockchip,rk3399-dmc.txt3 - compatible: "rockchip,rk3399-dmc", "syscon"
18 dmc: dmc {
20 compatible = "rockchip,rk3399-dmc";
35 &dmc {
H A Drockchip,rk3288-dmc.txt3 - compatible: "rockchip,rk3288-dmc", "syscon"
18 -logic-supply: this driver should adjust VDD_LOGIC according to dmc frequency, so need get logic-su…
113 dmc: dmc@ff610000 {
114 compatible = "rockchip,rk3288-dmc", "syscon";
132 &dmc {
/rk3399_rockchip-uboot/arch/arm/dts/
H A Drk3368-px5-evb-u-boot.dtsi16 &dmc {
21 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
40 &dmc {
H A Drk3368-lion-u-boot.dtsi29 &dmc {
42 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
H A Drv1108-u-boot.dtsi11 &dmc {
H A Drk3368-sheep-u-boot.dtsi15 &dmc {
H A Drk3368-geekbox-u-boot.dtsi15 &dmc {
H A Drk3399pro-npu-evb.dts21 &dmc {
H A Drv1108-sdram-ddr3-400.dtsi7 &dmc {
H A Drk3288-miqi.dts19 &dmc {
H A Drk3036-sdk-u-boot.dtsi5 &dmc {
H A Drk322x-u-boot.dtsi31 &dmc {
H A Drk3288-popmetal.dts19 &dmc {
H A Drk3288-fennec.dts19 &dmc {
H A Drk3368-u-boot.dtsi47 &dmc {
H A Drk3066a-evb.dts95 &dmc {
96 compatible = "rockchip,rk3066-dmc", "syscon";
H A Drk3066a-mk808.dts95 &dmc {
96 compatible = "rockchip,rk3066-dmc", "syscon";
H A Drk3128-u-boot.dtsi23 &dmc {
H A Drk3288-evb.dts36 &dmc {
/rk3399_rockchip-uboot/drivers/power/dvfs/
H A Drockchip_wtemp_dvfs.c116 struct pm_element *dmc; member
500 ofnode cpus, cpu, dmc; in wtemp_dvfs_ofdata_to_platdata() local
536 priv->dmc = &pm_dmc; in wtemp_dvfs_ofdata_to_platdata()
537 dmc = ofnode_path(FDT_PATH_DMC); in wtemp_dvfs_ofdata_to_platdata()
538 if (!ofnode_valid(dmc)) { in wtemp_dvfs_ofdata_to_platdata()
547 ret = __wtemp_common_ofdata_to_platdata(dmc, priv->dmc); in wtemp_dvfs_ofdata_to_platdata()
551 priv->dmc->lmt.ltemp_repeat = in wtemp_dvfs_ofdata_to_platdata()
553 priv->dmc->lmt.htemp_repeat = in wtemp_dvfs_ofdata_to_platdata()
556 list_add_tail(&priv->dmc->node, &pm_e_head); in wtemp_dvfs_ofdata_to_platdata()
587 priv->dmc->lmt.tztemp_limit = true; in wtemp_dvfs_ofdata_to_platdata()
[all …]
/rk3399_rockchip-uboot/drivers/ram/
H A Ddmc-uclass.c8 UCLASS_DRIVER(dmc) = {
H A DMakefile15 obj-$(CONFIG_DM_DMC) += dmc-uclass.o

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