| /rk3399_rockchip-uboot/arch/arm/lib/ |
| H A D | lib1funcs.S | 28 .macro ARM_DIV_BODY dividend, divisor, result, curbit
32 clz \curbit, \divisor
36 mov \divisor, \divisor, lsl \result
42 @ Initially shift the divisor left 3 bits if possible,
46 tst \divisor, #0xe0000000
47 moveq \divisor, \divisor, lsl #3
51 @ Unless the divisor is very big, shift it up in multiples of
53 @ division loop. Continue shifting until the divisor is
55 1: cmp \divisor, #0x10000000
56 cmplo \divisor, \dividend
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| H A D | div64.S | 54 bls 9f @ divisor is 0 or 1
56 beq 8f @ divisor is power of 2
63 @ Align divisor with upper part of dividend.
64 @ The aligned divisor is stored in yl preserving the original.
106 @ divisor for comparisons, considering the carry-out bit as well.
143 @ divisor at this point since divisor can not be smaller than 3 here.
151 8: @ Division by a power of 2: determine what that divisor order is
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| /rk3399_rockchip-uboot/lib/ |
| H A D | div64.c | 64 s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder) in div_s64_rem() argument
69 quotient = div_u64_rem(-dividend, abs(divisor), (u32 *)remainder); in div_s64_rem()
71 if (divisor > 0) in div_s64_rem()
74 quotient = div_u64_rem(dividend, abs(divisor), (u32 *)remainder); in div_s64_rem()
75 if (divisor < 0) in div_s64_rem()
95 u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder) in div64_u64_rem() argument
97 u32 high = divisor >> 32; in div64_u64_rem()
102 quot = div_u64_rem(dividend, divisor, &rem32); in div64_u64_rem()
106 quot = div_u64(dividend >> n, divisor >> n); in div64_u64_rem()
111 *remainder = dividend - quot * divisor; in div64_u64_rem()
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| /rk3399_rockchip-uboot/include/linux/ |
| H A D | math64.h | 19 static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder) in div_u64_rem() argument
21 *remainder = dividend % divisor; in div_u64_rem()
22 return dividend / divisor; in div_u64_rem()
28 static inline s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder) in div_s64_rem() argument
30 *remainder = dividend % divisor; in div_s64_rem()
31 return dividend / divisor; in div_s64_rem()
37 static inline u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder) in div64_u64_rem() argument
39 *remainder = dividend % divisor; in div64_u64_rem()
40 return dividend / divisor; in div64_u64_rem()
46 static inline u64 div64_u64(u64 dividend, u64 divisor) in div64_u64() argument
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| H A D | kernel.h | 90 #define DIV_ROUND_CLOSEST(x, divisor)( \ argument
93 typeof(divisor) __d = divisor; \
95 ((typeof(divisor))-1) > 0 || (__x) > 0) ? \
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| /rk3399_rockchip-uboot/arch/arm/mach-uniphier/debug-uart/ |
| H A D | debug-uart.c | 33 unsigned int divisor; in _debug_uart_init() local
38 divisor = uniphier_ld4_debug_uart_init(); in _debug_uart_init()
43 divisor = uniphier_pro4_debug_uart_init(); in _debug_uart_init()
48 divisor = uniphier_sld8_debug_uart_init(); in _debug_uart_init()
53 divisor = uniphier_pro5_debug_uart_init(); in _debug_uart_init()
58 divisor = uniphier_pxs2_debug_uart_init(); in _debug_uart_init()
63 divisor = uniphier_ld6b_debug_uart_init(); in _debug_uart_init()
69 divisor = uniphier_ld20_debug_uart_init(); in _debug_uart_init()
78 writel(divisor, base + UNIPHIER_UART_LDR); in _debug_uart_init()
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| /rk3399_rockchip-uboot/board/compulab/common/ |
| H A D | omap3_display.c | 57 .divisor = 12 | (1 << 16),
69 .divisor = 8 | (1 << 16),
81 .divisor = 5 | (1 << 16),
93 .divisor = 4 | (1 << 16),
105 .divisor = 3 | (1 << 16),
117 .divisor = 3 | (1 << 16),
129 .divisor = 10 | (1 << 10),
246 int divisor, pixclock_val; in parse_pixclock() local
250 divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val); in parse_pixclock()
252 if (divisor <= 1) in parse_pixclock()
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| /rk3399_rockchip-uboot/drivers/serial/ |
| H A D | serial_pl01x.c | 110 unsigned int divisor; in pl01x_generic_setbrg() local
117 divisor = UART_PL010_BAUD_9600; in pl01x_generic_setbrg()
120 divisor = UART_PL010_BAUD_19200; in pl01x_generic_setbrg()
123 divisor = UART_PL010_BAUD_38400; in pl01x_generic_setbrg()
126 divisor = UART_PL010_BAUD_57600; in pl01x_generic_setbrg()
129 divisor = UART_PL010_BAUD_115200; in pl01x_generic_setbrg()
132 divisor = UART_PL010_BAUD_38400; in pl01x_generic_setbrg()
135 writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm); in pl01x_generic_setbrg()
136 writel(divisor & 0xff, ®s->pl010_lcrl); in pl01x_generic_setbrg()
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| H A D | serial_mpc8xx.c | 41 int divisor = (gd->cpu_clk + 8 * gd->baudrate) / 16 / gd->baudrate; in serial_setdivisor() local
43 if (divisor / 16 > 0x1000) { in serial_setdivisor()
45 divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600; in serial_setdivisor()
48 divisor /= CONFIG_SYS_BRGCLK_PRESCALE; in serial_setdivisor()
50 if (divisor <= 0x1000) in serial_setdivisor()
51 out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) | CPM_BRG_EN); in serial_setdivisor()
53 out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) | CPM_BRG_EN | in serial_setdivisor()
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| H A D | atmel_usart.c | 33 unsigned long divisor; in atmel_serial_setbrg_internal() local
42 divisor = (usart_hz / 16 + baudrate / 2) / baudrate; in atmel_serial_setbrg_internal()
43 writel(USART3_BF(CD, divisor), &usart->brgr); in atmel_serial_setbrg_internal()
150 unsigned long divisor; in _atmel_serial_set_brg() local
152 divisor = (usart_clk_rate / 16 + baudrate / 2) / baudrate; in _atmel_serial_set_brg()
153 writel(USART3_BF(CD, divisor), &usart->brgr); in _atmel_serial_set_brg()
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| H A D | serial_uniphier.c | 50 unsigned int divisor; in uniphier_serial_setbrg() local
52 divisor = DIV_ROUND_CLOSEST(priv->uartclk, mode_x_div * baudrate); in uniphier_serial_setbrg()
54 writel(divisor, &port->dlr); in uniphier_serial_setbrg()
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| H A D | altera_uart.c | 26 u32 divisor; /* Baud rate divisor reg */ member
42 writel(div, ®s->divisor); in altera_uart_setbrg()
134 writel(div, ®s->divisor); in _debug_uart_init()
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/serial/ |
| H A D | bcm2835-aux-uart.txt | 7 rate divisor)
10 - skip-init: if present, the baud rate divisor is not changed
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| H A D | pl01x.txt | 7 rate divisor)
10 - skip-init: if present, the baud rate divisor is not changed
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| /rk3399_rockchip-uboot/drivers/clk/aspeed/ |
| H A D | clk_ast2500.c | 254 u32 divisor; in ast2500_configure_mac() local
268 divisor = hpll_rate / required_rate; in ast2500_configure_mac()
270 if (divisor < 4) { in ast2500_configure_mac()
273 divisor = 4; in ast2500_configure_mac()
274 } else if (divisor > 16) { in ast2500_configure_mac()
277 divisor = 16; in ast2500_configure_mac()
295 ((divisor - 2) / 2) << SCU_MACCLK_SHIFT); in ast2500_configure_mac()
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| /rk3399_rockchip-uboot/drivers/mmc/ |
| H A D | uniphier-sd.c | 545 unsigned int divisor; in uniphier_sd_set_clk_rate() local
551 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); in uniphier_sd_set_clk_rate()
553 if (divisor <= 1) in uniphier_sd_set_clk_rate()
555 else if (divisor <= 2) in uniphier_sd_set_clk_rate()
557 else if (divisor <= 4) in uniphier_sd_set_clk_rate()
559 else if (divisor <= 8) in uniphier_sd_set_clk_rate()
561 else if (divisor <= 16) in uniphier_sd_set_clk_rate()
563 else if (divisor <= 32) in uniphier_sd_set_clk_rate()
565 else if (divisor <= 64) in uniphier_sd_set_clk_rate()
567 else if (divisor <= 128) in uniphier_sd_set_clk_rate()
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| /rk3399_rockchip-uboot/include/ |
| H A D | div64.h | 198 extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
237 static inline uint64_t lldiv(uint64_t dividend, uint32_t divisor) in lldiv() argument
240 do_div(__res, divisor); in lldiv()
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| /rk3399_rockchip-uboot/drivers/qe/ |
| H A D | qe.c | 283 u32 divisor; in qe_set_brg() local
291 divisor = (BRG_CLK / rate); in qe_set_brg()
292 if (divisor > QE_BRGC_DIVISOR_MAX + 1) { in qe_set_brg()
294 divisor /= 16; in qe_set_brg()
297 *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE; in qe_set_brg()
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| /rk3399_rockchip-uboot/board/teejet/mt_ventoux/ |
| H A D | mt_ventoux.c | 67 .divisor = 0x00010033, /* 9 Mhz Pixel Clock */
78 .divisor = 0x0001000E, /* 36Mhz Pixel Clock */
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap3/ |
| H A D | dss.h | 70 u32 divisor; /* 0x70 */ member
206 u32 divisor; member
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| /rk3399_rockchip-uboot/board/htkw/mcx/ |
| H A D | mcx.c | 116 .divisor = 0x0001000E,
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| /rk3399_rockchip-uboot/fs/ubifs/ |
| H A D | budget.c | 636 int divisor, factor, f; in ubifs_reported_space() local
653 divisor = UBIFS_MAX_DATA_NODE_SZ; in ubifs_reported_space()
654 divisor += (c->max_idx_node_sz * 3) / (f - 1); in ubifs_reported_space()
656 return div_u64(free, divisor); in ubifs_reported_space()
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| /rk3399_rockchip-uboot/drivers/video/ |
| H A D | omap3_dss.c | 113 writel(panel_cfg->divisor, &dispc->divisor); in omap3_dss_panel_config()
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| /rk3399_rockchip-uboot/board/topic/zynq/zynq-topic-miamiplus/ |
| H A D | ps7_regs.txt | 1 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 (433 MHz)
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| /rk3399_rockchip-uboot/board/topic/zynq/zynq-topic-miamilite/ |
| H A D | ps7_regs.txt | 1 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?)
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