Searched refs:div4 (Results 1 – 4 of 4) sorted by relevance
33 unsigned int div4; member69 unsigned int div4; member
39 u32 div4; /* 60 */ member
126 "cga-pll1-div4";141 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
133 offset = pllctl_reg(data->pll, div4) + (i - 3); in configure_main_pll()