Searched refs:ctl_reg (Results 1 – 5 of 5) sorted by relevance
44 u32 *cfg_reg, *ctl_reg; in mx3_setup_sdram_bank() local51 ctl_reg = &esdc->esdctl0; in mx3_setup_sdram_bank()55 ctl_reg = &esdc->esdctl1; in mx3_setup_sdram_bank()84 ctl_reg); in mx3_setup_sdram_bank()89 ctl_reg); in mx3_setup_sdram_bank()97 ctl_reg); in mx3_setup_sdram_bank()102 ctl_reg); in mx3_setup_sdram_bank()107 ctl_reg); in mx3_setup_sdram_bank()116 ctl_reg); in mx3_setup_sdram_bank()
37 union FM_CTL_T ctl_reg; in nandc_init() local41 ctl_reg.d32 = 0; in nandc_init()46 ctl_reg.V9.wp = 1; in nandc_init()47 ctl_reg.V9.sif_read_delay = 2; in nandc_init()48 nandc_writel(ctl_reg.d32, NANDC_V9_FMCTL); in nandc_init()52 ctl_reg.V6.wp = 1; in nandc_init()53 nandc_writel(ctl_reg.d32, NANDC_FMCTL); in nandc_init()
247 u32 ctl_reg; in dnet_phy_init() local300 ctl_reg = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG); in dnet_phy_init()303 ctl_reg &= ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP); in dnet_phy_init()305 ctl_reg |= DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP; in dnet_phy_init()307 dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg); in dnet_phy_init()
32 unsigned char ctl_reg; member
63 port[num].ctl_reg = 0x08; /*Default value of control reg */ in sata_bus_softreset()64 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); in sata_bus_softreset()66 writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr); in sata_bus_softreset()68 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); in sata_bus_softreset()