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Searched refs:axi (Results 1 – 25 of 35) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Dclock_sun4i.c122 int axi, ahb, apb0; in clock_set_pll1() local
135 axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ in clock_set_pll1()
136 ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */ in clock_set_pll1()
139 printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); in clock_set_pll1()
142 axi = axi - 1; in clock_set_pll1()
163 writel(axi << AXI_DIV_SHIFT | in clock_set_pll1()
174 writel(axi << AXI_DIV_SHIFT | in clock_set_pll1()
/rk3399_rockchip-uboot/arch/mips/dts/
H A Dimg,boston.dts49 compatible = "xlnx,axi-pcie-host-1.00.a";
78 compatible = "xlnx,axi-pcie-host-1.00.a";
106 compatible = "xlnx,axi-pcie-host-1.00.a";
H A Dnexys4ddr.dts36 xlnx,s-axi-id-width = <0x1>;
/rk3399_rockchip-uboot/drivers/pci/
H A Dpci_tegra.c807 unsigned long fpci, axi, size; local
814 axi = pcie->cs.start;
816 afi_writel(pcie, axi, AFI_AXI_BAR0_START);
827 axi = io->phys_start;
829 afi_writel(pcie, axi, AFI_AXI_BAR1_START);
836 axi = pref->phys_start;
838 afi_writel(pcie, axi, AFI_AXI_BAR2_START);
845 axi = mem->phys_start;
847 afi_writel(pcie, axi, AFI_AXI_BAR3_START);
/rk3399_rockchip-uboot/board/aristainetos/
H A Daristainetos2.cfg34 #include "axi.cfg"
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dsun5i.dtsi191 axi: axi@01c20054 { label
193 compatible = "allwinner,sun4i-a10-axi-clk";
196 clock-output-names = "axi";
203 clocks = <&axi>, <&cpu>, <&pll6 1>;
231 compatible = "allwinner,sun4i-a10-axi-gates-clk";
233 clocks = <&axi>;
H A Dsun5i-gr8.dtsi191 axi: axi@01c20054 { label
193 compatible = "allwinner,sun4i-a10-axi-clk";
196 clock-output-names = "axi";
203 clocks = <&axi>, <&cpu>, <&pll6 1>;
233 clocks = <&axi>;
H A Dsun8i-a23-a33.dtsi154 axi: axi_clk@01c20050 { label
156 compatible = "allwinner,sun8i-a23-axi-clk";
159 clock-output-names = "axi";
166 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
H A Dsun4i-a10.dtsi291 axi: axi@01c20054 { label
293 compatible = "allwinner,sun4i-a10-axi-clk";
296 clock-output-names = "axi";
301 compatible = "allwinner,sun4i-a10-axi-gates-clk";
303 clocks = <&axi>;
312 clocks = <&axi>;
H A Dimx6sx.dtsi1120 clock-names = "disp-axi", "csi_mclk", "dcic";
1129 clock-names = "pxp-axi", "disp-axi";
1139 clock-names = "disp-axi", "csi_mclk", "dcic";
1150 clock-names = "pix", "axi", "disp_axi";
1161 clock-names = "pix", "axi", "disp_axi";
H A Dsun6i-a31.dtsi226 axi: axi@01c20050 { label
228 compatible = "allwinner,sun4i-a10-axi-clk";
231 clock-output-names = "axi";
238 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
H A Dzynqmp-ep108.dts233 xlnx,axi-clock-freq = <200000000>;
H A Drk3588.dtsi391 snps,axi-config = <&gmac0_stmmac_axi_setup>;
402 gmac0_stmmac_axi_setup: stmmac-axi-config {
H A Dsun7i-a20.dtsi301 axi: axi@01c20054 { label
303 compatible = "allwinner,sun4i-a10-axi-clk";
306 clock-output-names = "axi";
313 clocks = <&axi>, <&pll6 3>, <&pll6 1>;
H A Drk3528.dtsi1785 snps,axi-config = <&gmac0_stmmac_axi_setup>;
1814 gmac0_stmmac_axi_setup: stmmac-axi-config {
1848 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1860 gmac1_stmmac_axi_setup: stmmac-axi-config {
1886 clock-names = "core", "bus", "axi", "block", "timer";
1890 reset-names = "core", "bus", "axi", "block", "timer";
H A Drk3506.dtsi973 snps,axi-config = <&gmac0_stmmac_axi_setup>;
986 gmac0_stmmac_axi_setup: stmmac-axi-config {
1024 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1037 gmac1_stmmac_axi_setup: stmmac-axi-config {
H A Dimx6sll.dtsi627 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
670 clock-names = "pix", "axi", "disp_axi";
H A Drk3562.dtsi1248 reset-names = "axi",
1890 clock-names = "core", "bus", "axi", "block", "timer";
1894 reset-names = "core", "bus", "axi", "block", "timer";
2122 snps,axi-config = <&gmac0_stmmac_axi_setup>;
2133 gmac0_stmmac_axi_setup: stmmac-axi-config {
H A Drk3568.dtsi1208 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1219 gmac1_stmmac_axi_setup: stmmac-axi-config {
1785 snps,axi-config = <&gmac0_stmmac_axi_setup>;
1796 gmac0_stmmac_axi_setup: stmmac-axi-config {
1866 clock-names = "core", "bus", "axi", "block", "timer";
H A Dimx6ull.dtsi989 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
1000 clock-names = "pix", "axi", "disp_axi";
H A Drv1103b.dtsi521 snps,axi-config = <&stmmac_axi_setup>;
553 stmmac_axi_setup: stmmac-axi-config {
H A Dimx7ulp.dtsi469 clock-names = "axi", "pix", "disp_axi";
H A Drv1106.dtsi1062 snps,axi-config = <&stmmac_axi_setup>;
1089 stmmac_axi_setup: stmmac-axi-config {
H A Drk3288.dtsi722 reset-names = "axi", "ahb", "dclk";
766 reset-names = "axi", "ahb", "dclk";
/rk3399_rockchip-uboot/drivers/video/drm/
H A Drockchip_crtc.h37 int (*reset) (struct udevice *dev, u32 axi, u32 vp_mask, u32 plane_mask);

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