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Searched refs:addressing (Results 1 – 17 of 17) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Demif-common.c554 const struct lpddr2_addressing *addressing, in get_sdram_config_reg() argument
567 config_reg |= addressing->row_sz[cs0_device->io_width] << in get_sdram_config_reg()
570 config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT; in get_sdram_config_reg()
575 config_reg |= addressing->col_sz[cs0_device->io_width] << in get_sdram_config_reg()
582 const struct lpddr2_addressing *addressing) in get_sdram_ref_ctrl() argument
590 val = addressing->t_REFI_us_x10 * freq_khz / 10000; in get_sdram_ref_ctrl()
598 const struct lpddr2_addressing *addressing) in get_sdram_tim_1_reg() argument
604 if (addressing->num_banks == BANKS8) in get_sdram_tim_1_reg()
656 const struct lpddr2_addressing *addressing) in get_sdram_tim_3_reg() argument
659 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF); in get_sdram_tim_3_reg()
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/rk3399_rockchip-uboot/drivers/ddr/fsl/
H A Dddr3_dimm_params.c169 pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12; in ddr_compute_dimm_parameters()
170 pdimm->n_col_addr = (spd->addressing & 0x7) + 9; in ddr_compute_dimm_parameters()
H A Dddr4_dimm_params.c213 pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12; in ddr_compute_dimm_parameters()
214 pdimm->n_col_addr = (spd->addressing & 0x7) + 9; in ddr_compute_dimm_parameters()
H A Dinteractive.c1239 PRINT_NXS(5, spd->addressing, in ddr3_spd_dump()
1431 PRINT_NXS(5, spd->addressing, in ddr4_spd_dump()
/rk3399_rockchip-uboot/doc/SPI/
H A Dstatus.txt11 - Bank Address Register (Accessing flashes > 16Mbytes in 3-byte addressing)
/rk3399_rockchip-uboot/include/
H A Dddr_spd.h184 unsigned char addressing; /* 5 SDRAM Addressing */ member
299 uint8_t addressing; /* 5 Addressing */ member
/rk3399_rockchip-uboot/doc/
H A DREADME.sata14 Supports 48-bit addressing
H A DREADME.dns9 locating and addressing these devices world-wide. An often used analogy to
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Drockchip,rk3368-dmc.txt45 controls the decoding of physical addresses to DRAM addressing (i.e. how
/rk3399_rockchip-uboot/board/freescale/ls1021aqds/
H A DREADME33 - 40-bit physical addressing
/rk3399_rockchip-uboot/board/freescale/ls1021atwr/
H A DREADME33 - 40-bit physical addressing
/rk3399_rockchip-uboot/arch/arm/mach-keystone/
H A Dddr3_spd.c183 spd->pagesize = (buf->addressing & 0x07) + 1; in ddrtimingcalculation()
/rk3399_rockchip-uboot/drivers/mtd/spi/
H A DKconfig95 which has size > 16MiB in 3-byte addressing.
/rk3399_rockchip-uboot/drivers/i2c/
H A DKconfig188 _ 7-bit and 10-bit addressing mode
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A DKconfig249 The default setting for QSPI AHB bus just support 3bytes addressing.
/rk3399_rockchip-uboot/drivers/misc/
H A DKconfig66 SoCs: accesses can either be made using byte addressing and a length
/rk3399_rockchip-uboot/
H A DREADME981 Define this to enable 32 bit addressing