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/rk3399_rockchip-uboot/doc/
H A DREADME.unaligned-memory-access.txt8 when it comes to memory access. This document presents some details about
13 The definition of an unaligned access
20 access.
22 The above may seem a little vague, as memory access can happen in different
26 which will compile to multiple-byte memory access instructions, namely when
41 of memory access. However, we must consider ALL supported architectures;
46 Why unaligned access is bad
49 The effects of performing an unaligned memory access vary from architecture
56 happen. The exception handler is able to correct the unaligned access,
60 unaligned access to be corrected.
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H A DREADME.omap-ulpi-viewport4 any ulpi phy port access on omap platform.
7 register which offers the ulpi phy access so
/rk3399_rockchip-uboot/drivers/spi/
H A DKconfig12 the SPI uclass. Drivers provide methods to access the SPI
32 access the SPI NOR flash on platforms embedding this Altera
40 used to access the SPI flash on AE3XX and AE250 platforms embedding
48 to access SPI NOR flash and other SPI peripherals. This driver
57 many AT91 (ARM) chips. This driver can be used to access
65 access the SPI NOR flash on platforms embedding this Broadcom
73 access the SPI NOR flash on platforms embedding these Broadcom
80 be used to access the SPI flash on platforms embedding this
87 used to access the SPI NOR flash on platforms embedding this
94 access the SPI NOR flash on platforms embedding this Designware
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/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Drockchip,rk3399-dmc.txt4 - rockchip,cru: this driver should access cru regs, so need get cru here
5 - rockchip,pmucru: this driver should access pmucru regs, so need get pmucru here
6 - rockchip,pmugrf: this driver should access pmugrf regs, so need get pmugrf here
7 - rockchip,pmusgrf: this driver should access pmusgrf regs, so need get pmusgrf here
8 - rockchip,cic: this driver should access cic regs, so need get cic here
H A Drockchip,rk3288-dmc.txt4 - rockchip,cru: this driver should access cru regs, so need get cru here
5 - rockchip,grf: this driver should access grf regs, so need get grf here
6 - rockchip,pmu: this driver should access pmu regs, so need get pmu here
7 - rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here
8 - rockchip,noc: this driver should access noc regs, so need get noc here
13 pclk_ddrupctl0: support clock for access protocol controller registers of channel 0
14 pclk_publ0: support clock for access phy controller registers of channel 0
15 pclk_ddrupctl1: support clock for access protocol controller registers of channel 1
16 pclk_publ1: support clock for access phy controller registers of channel 1
/rk3399_rockchip-uboot/env/
H A Dflags.c100 const char *env_flags_get_varaccess_name(enum env_flags_varaccess access) in env_flags_get_varaccess_name() argument
102 return env_flags_varaccess_names[access]; in env_flags_get_varaccess_name()
133 char *access; in env_flags_parse_varaccess() local
138 access = strchr(env_flags_varaccess_rep, in env_flags_parse_varaccess()
141 if (access != NULL) in env_flags_parse_varaccess()
143 (access - &env_flags_varaccess_rep[0]); in env_flags_parse_varaccess()
366 enum env_flags_varaccess access; in env_flags_validate_varaccess() local
369 access = env_flags_get_varaccess(name); in env_flags_validate_varaccess()
370 access_mask = env_flags_varaccess_mask[access]; in env_flags_validate_varaccess()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3288/
H A DKconfig9 WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
20 keyboard and mouse access.
29 EC (Cortex-M3) to provide access to the keyboard and battery
40 provide access to display pins, I2C, SPI, UART and GPIOs.
51 access to display pins, I2C, SPI, UART and GPIOs.
60 provide access to display pins, I2C, SPI, UART and GPIOs.
69 provide access to display pins, I2C, SPI, UART and GPIOs.
77 has 1 or 2 GiB SDRAM. Expansion connectors provide access to
95 2GB DDR3. Expansion connectors provide access to I2C, SPI, UART,
121 provide access to display pins, I2C, SPI, UART and GPIOs.
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/rk3399_rockchip-uboot/board/gateworks/gw_ventana/
H A DKconfig15 Provides access to EEPROM configuration on Gateworks Ventana
20 Provides access to the GSC configuration:
/rk3399_rockchip-uboot/arch/arm/dts/
H A Domap-gpmc-smsc9221.dtsi44 gpmc,access-ns = <36>;
45 gpmc,page-burst-access-ns = <0>;
49 gpmc,wr-access-ns = <42>;
/rk3399_rockchip-uboot/drivers/tpm/
H A Dtpm_tis_lpc.c40 u32 access; member
400 tpm_write_word(priv, TIS_ACCESS_REQUEST_USE, &regs[locality].access); in tpm_tis_lpc_open()
403 ret = tis_wait_reg(priv, &regs[locality].access, in tpm_tis_lpc_open()
423 if (tpm_read_word(priv, &regs[locality].access) & in tpm_tis_lpc_close()
426 &regs[locality].access); in tpm_tis_lpc_close()
428 if (tis_wait_reg(priv, &regs[locality].access, in tpm_tis_lpc_close()
/rk3399_rockchip-uboot/drivers/mtd/
H A DKconfig25 Enable write access to nand & spi nand & spi nor
63 This enables access to Altera EPCQ/EPCS flash chips using the
72 This enables access to Microchip PIC32 internal non-CFI flash
79 This enables access to Hyperflash memory through the Renesas
/rk3399_rockchip-uboot/drivers/crypto/fsl/
H A DKconfig36 bool "Big-endian access to Freescale Secure Boot"
47 bool "Little-endian access to Freescale Secure Boot"
/rk3399_rockchip-uboot/drivers/mmc/
H A Dmmc_boot.c101 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) in mmc_set_part_conf() argument
108 EXT_CSD_PARTITION_ACCESS(access); in mmc_set_part_conf()
/rk3399_rockchip-uboot/arch/arm/cpu/armv7m/
H A Dconfig.mk8 PLATFORM_CPPFLAGS += -march=armv7-m -mthumb -mno-unaligned-access
/rk3399_rockchip-uboot/drivers/misc/
H A DKconfig14 access the device.
23 access the device.
32 access the device.
65 Enable (read-only) access for the e-fuse block found in Rockchip
152 Enable command-line access to the Chrome OS EC (Embedded
161 Enable access to the Chrome OS EC. This is a separate
163 provides access to the keyboard, some internal storage and may
164 control access to the battery and main PMIC depending on the
165 device. You can use the 'crosec' command to access it.
171 Enable I2C access to the Chrome OS EC. This is used on older
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/rk3399_rockchip-uboot/arch/arm/cpu/armv7/
H A Dconfig.mk12 PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc86xx/
H A DKconfig58 int "Number of local access windows"
61 Number of local access windows. This is fixed per SoC.
/rk3399_rockchip-uboot/tools/env/
H A DREADME2 This is a demo implementation of a Linux command line tool to access
45 be used to access the environment.
62 drivers, a lock file at /var/lock/fw_printenv.lock is used to serialize access
/rk3399_rockchip-uboot/fs/yaffs2/
H A DKconfig4 This provides access to YAFFS2 filesystems. Yet Another Flash
/rk3399_rockchip-uboot/fs/cramfs/
H A DKconfig7 access.
/rk3399_rockchip-uboot/drivers/usb/emul/
H A DKconfig5 Since sandbox does not have access to a real USB bus, it is possible
/rk3399_rockchip-uboot/board/cavium/thunderx/
H A DKconfig24 devices access, low level environment query, boot device layout
/rk3399_rockchip-uboot/doc/device-tree-bindings/gpio/
H A Dnvidia,tegra186-gpio.txt14 a) Security registers, which allow configuration of allowed access to the GPIO
20 that wishes to configure access to the GPIO registers needs access to these
22 need access to these registers.
26 address space, each of which access the same underlying state. See the hardware
27 documentation for rationale. Any particular GPIO client is expected to access
/rk3399_rockchip-uboot/fs/cbfs/
H A DKconfig8 CMD_CBFS to get command-line access.
/rk3399_rockchip-uboot/drivers/clk/tegra/
H A DKconfig6 register access to the Tegra CAR (Clock And Reset controller).

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