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Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL8 (Results 1 – 1 of 1) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra210/
H A Dxusb-padctl.c203 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c macro
242 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
244 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
329 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
332 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
338 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
348 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
350 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
356 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
366 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
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