| /rk3399_rockchip-uboot/doc/ |
| H A D | README.mpc85xxcds | 88 SW2[2] on the carrier card before resetting the board in order to set the 101 The first two bits of SW2 control how flash is used on the board: 105 SW2=00XXXXXX FLASH: Boot bank 1, bank 2 available. 114 connected.. By convention, the user-specific bits of SW2 are used to 119 SW2=xxxxxx00 PCI SLOT INFORM: The CDS carrier is in slot0 of the Arcadia 133 SW2=0x1111yy x=Flash bank, yy=PCI slot 158 SW2=01000111 172 SW2=10011111
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| H A D | README.b4860qds | 123 SW2 ON ON ON ON ON ON OFF OFF 135 SW2 [1.1] = 1 139 SW2 [1.1] = 0 148 SW2 ON OFF ON OFF ON ON OFF OFF 160 SW2 [1.1] = 1 164 SW2 [1.1] = 0
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| H A D | README.uniphier | 142 SW2 OFF(1)/ON(0) Description
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| /rk3399_rockchip-uboot/board/sbc8548/ |
| H A D | README | 36 card. [The above discussion assumes that the SW2[1-4] has not been changed 194 alternate setting, you also need to switch SW2.8 to ON. 207 SW2.1 CFG_SYS_PLL0 1 0* 208 SW2.2 CFG_SYS_PLL1 1* 0 209 SW2.3 CFG_SYS_PLL2 1* 0 210 SW2.4 CFG_SYS_PLL3 1 0* 211 SW2.5 CFG_CORE_PLL0 1* 0 212 SW2.6 CFG_CORE_PLL1 1 0* 213 SW2.7 CFG_CORE_PLL2 1* 0 214 SW2.8 CFG_ROM_LOC1 1 0*
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| /rk3399_rockchip-uboot/board/freescale/t104xrdb/ |
| H A D | README | 287 SW2: 10111011 292 SW2: 00111011 297 SW2: 10111011 302 SW2: 00111011 309 SW2: 10111001 314 SW2: 00111001 319 SW2: 10111001 324 SW2: 00111001
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| /rk3399_rockchip-uboot/board/freescale/mx35pdk/ |
| H A D | README | 14 switch the boot device with the switches SW1-SW2 on the Personality board, 77 (SW1-SW2) and on the DEBUG board (SW4-SW10). 105 SW2 all off
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| /rk3399_rockchip-uboot/board/freescale/mpc8536ds/ |
| H A D | README | 36 SW2[5-8] = 1011 70 SW2[5-8] = 0111 123 SW2[5-8] = 0110
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| /rk3399_rockchip-uboot/include/power/ |
| H A D | mc34vr500_pmic.h | 167 SW2, enumerator
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| /rk3399_rockchip-uboot/board/freescale/t208xrdb/ |
| H A D | README | 142 SW2[1:8] = '10111111' 154 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot 173 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot 184 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot 193 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
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| /rk3399_rockchip-uboot/board/freescale/mpc837xemds/ |
| H A D | README | 18 SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. 19 SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
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| /rk3399_rockchip-uboot/board/freescale/t102xrdb/ |
| H A D | README | 194 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot 196 set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot 223 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot 237 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot 248 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
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| /rk3399_rockchip-uboot/board/freescale/t208xqds/ |
| H A D | README | 171 set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot 190 set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot 201 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot 212 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
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| /rk3399_rockchip-uboot/board/freescale/mpc8641hpcn/ |
| H A D | README | 33 SW2(1-4) = 1100 CONFIG_SYS_CCBPLL = 0010 :: 2X 41 SW2(5-8) = 1110 CONFIG_SYS_BOOTLOC = 1110 :: boot 16-bit localbus
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| /rk3399_rockchip-uboot/board/freescale/t102xqds/ |
| H A D | README | 220 set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot 239 set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot 250 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot 261 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
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| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | imx7ulp-evk.dts | 115 sw2_reg: SW2 { 116 regulator-name = "SW2";
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| H A D | tegra30-apalis.dts | 130 /* SW2: +V1.05 */
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| /rk3399_rockchip-uboot/board/freescale/p1010rdb/ |
| H A D | README.P1010RDB-PB | 65 SW2[1:8]= 11011000 91 SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s)
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| /rk3399_rockchip-uboot/board/freescale/t4qds/ |
| H A D | README | 189 SW2[1.1] = 0 194 SW2[1.1] = 0
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