| /rk3399_rockchip-uboot/doc/ |
| H A D | README.pblimage | 41 Change SW1[1:5] = off off on off on. 49 Change SW1[1:5] = off off on on off. 58 Change SW1[1:5] = off on off off on
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| H A D | README.mpc85xxcds | 132 SW1=01101100 157 SW1=10001111 171 SW1=11111101
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| H A D | README.b4860qds | 122 SW1 OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] 134 SW1 [1.1] = 0 138 SW1 [1.1] = 1 147 SW1 OFF[0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] 159 SW1 [1.1] = 0 163 SW1 [1.1] = 1
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| /rk3399_rockchip-uboot/board/freescale/p2041rdb/ |
| H A D | README | 37 SW1[1-5] = 10110 60 SW1[1-5] = 01100 85 SW1[1-5] = 10100
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| /rk3399_rockchip-uboot/board/freescale/t104xrdb/ |
| H A D | README | 286 SW1: 00010011 291 SW1: 10001000 296 SW1: 00100010 301 SW1: 00100000 308 SW1: 00010011 313 SW1: 10001000 318 SW1: 00100010 323 SW1: 00100000
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| /rk3399_rockchip-uboot/board/freescale/mx35pdk/ |
| H A D | README | 14 switch the boot device with the switches SW1-SW2 on the Personality board, 77 (SW1-SW2) and on the DEBUG board (SW4-SW10). 106 SW1 all off
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| /rk3399_rockchip-uboot/board/freescale/p1010rdb/ |
| H A D | README.P1010RDB-PB | 64 SW1[1:8]= 10101010 91 SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s) 153 set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board 157 set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
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| H A D | README.P1010RDB-PA | 125 or set SW1[8]= ON 127 SW1[8]= OFF: Upper bank used for booting start 128 SW1[8]= ON: Lower bank used for booting start
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| /rk3399_rockchip-uboot/include/power/ |
| H A D | mc34vr500_pmic.h | 166 SW1 = 0, enumerator
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| /rk3399_rockchip-uboot/board/freescale/t208xrdb/ |
| H A D | README | 141 SW1[1:8] = '00010011' 154 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot 173 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot 184 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot 193 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
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| /rk3399_rockchip-uboot/board/freescale/t102xrdb/ |
| H A D | README | 194 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot 196 set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot 223 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot 237 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot 248 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
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| /rk3399_rockchip-uboot/board/freescale/t208xqds/ |
| H A D | README | 171 set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot 190 set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot 201 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot 212 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
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| /rk3399_rockchip-uboot/board/freescale/mpc8641hpcn/ |
| H A D | README | 24 SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1 30 SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz
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| /rk3399_rockchip-uboot/board/freescale/m54455evb/ |
| H A D | README | 182 3.1 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL 183 SW1 Pin4: 0 - ULPI chip not in reset state or 1 - ULPI chip in reset state 184 SW1 Pin5: 0 - Full ATA Bus enabled, FEC Phy1 powered down 186 SW1 Pin6: 0 - FEC Phy0 active or 1 - FEC Phy0 powered down 187 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
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| /rk3399_rockchip-uboot/board/freescale/t102xqds/ |
| H A D | README | 220 set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot 239 set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot 250 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot 261 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
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| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | imx7ulp-evk.dts | 107 sw1_reg: SW1 { 108 regulator-name = "SW1";
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| H A D | tegra30-apalis.dts | 122 /* SW1: +V1.35_VDDIO_DDR */
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| /rk3399_rockchip-uboot/board/ti/ks2_evm/ |
| H A D | README | 97 to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode" 148 Once U-Boot prompt is available, Power OFF the EVM. Set the SW1 dip switch 168 Once U-Boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
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| /rk3399_rockchip-uboot/board/boundary/nitrogen6x/ |
| H A D | README.mx6qsabrelite | 34 the board). Make sure SW1 switch is at position "00", so that it can boot
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| /rk3399_rockchip-uboot/board/freescale/t4qds/ |
| H A D | README | 188 SW1[1:8] = 10000010 193 SW1[1:8] = 00100000
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