Searched refs:SERDES_CR_CTL (Results 1 – 1 of 1) sorted by relevance
| /rk3399_rockchip-uboot/board/highbank/ |
| H A D | ahci.c | 17 #define SERDES_CR_CTL 0x80a0 macro
61 while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) in combo_phy_read()
64 __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_START); in combo_phy_read()
65 while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) in combo_phy_read()
75 while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) in combo_phy_write()
79 __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_WR_RDN | CR_START); in combo_phy_write()
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