Searched refs:RC (Results 1 – 12 of 12) sorted by relevance
56 u32 dramsize, RC; in dram_init() local79 RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1; in dram_init()80 RC = (RC * 15) >> 4; in dram_init()83 out_be16(&dc->dcr, 0x8200 | RC); in dram_init()
31 u32 RC, dramsize; in dram_init() local33 RC = (CONFIG_SYS_CLK / 1000000) >> 1; in dram_init()34 RC = (RC * 15) >> 4; in dram_init()37 mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); in dram_init()
34 u32 RC, temp; in dram_init() local36 RC = (CONFIG_SYS_CLK / 1000000) >> 1; in dram_init()37 RC = (RC * 15) >> 4; in dram_init()40 mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); in dram_init()
26 #define RC 0x3400 /* 32bit */ macro
12 #define RC 0x3400 /* 32bit */ macro
51 writel(1 << 2, RCB_REG(RC)); in cpu_common_init()
45 * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
131 * It is an internal RC-based oscillator.
134 * the clock switched to an internal 16M RC oscillator. Under
79 PCIe controllers. The PCIe may works in RC or EP mode according to
465 setbits_le32(RCB_REG(RC), 1 << 2); in broadwell_pch_init()
623 Enable support for PCIE EP driver in SPL. The RC will download the