1*2f3f477bSSimon Glass /* 2*2f3f477bSSimon Glass * Copyright (c) 2016 Google, Inc 3*2f3f477bSSimon Glass * 4*2f3f477bSSimon Glass * SPDX-License-Identifier: GPL-2.0 5*2f3f477bSSimon Glass */ 6*2f3f477bSSimon Glass 7*2f3f477bSSimon Glass #ifndef __asm_arch_rcba_h 8*2f3f477bSSimon Glass #define __asm_arch_rcba_h 9*2f3f477bSSimon Glass 10*2f3f477bSSimon Glass #define PMSYNC_CONFIG 0x33c4 /* 32bit */ 11*2f3f477bSSimon Glass #define PMSYNC_CONFIG2 0x33cc /* 32bit */ 12*2f3f477bSSimon Glass 13*2f3f477bSSimon Glass #define DEEP_S3_POL 0x3328 /* 32bit */ 14*2f3f477bSSimon Glass #define DEEP_S3_EN_AC (1 << 0) 15*2f3f477bSSimon Glass #define DEEP_S3_EN_DC (1 << 1) 16*2f3f477bSSimon Glass #define DEEP_S5_POL 0x3330 /* 32bit */ 17*2f3f477bSSimon Glass #define DEEP_S5_EN_AC (1 << 14) 18*2f3f477bSSimon Glass #define DEEP_S5_EN_DC (1 << 15) 19*2f3f477bSSimon Glass #define DEEP_SX_CONFIG 0x3334 /* 32bit */ 20*2f3f477bSSimon Glass #define DEEP_SX_WAKE_PIN_EN (1 << 2) 21*2f3f477bSSimon Glass #define DEEP_SX_ACPRESENT_PD (1 << 1) 22*2f3f477bSSimon Glass #define DEEP_SX_GP27_PIN_EN (1 << 0) 23*2f3f477bSSimon Glass #define PMSYNC_CONFIG 0x33c4 /* 32bit */ 24*2f3f477bSSimon Glass #define PMSYNC_CONFIG2 0x33cc /* 32bit */ 25*2f3f477bSSimon Glass 26*2f3f477bSSimon Glass #define RC 0x3400 /* 32bit */ 27*2f3f477bSSimon Glass #define HPTC 0x3404 /* 32bit */ 28*2f3f477bSSimon Glass #define GCS 0x3410 /* 32bit */ 29*2f3f477bSSimon Glass #define BUC 0x3414 /* 32bit */ 30*2f3f477bSSimon Glass #define PCH_DISABLE_GBE (1 << 5) 31*2f3f477bSSimon Glass #define FD 0x3418 /* 32bit */ 32*2f3f477bSSimon Glass #define FDSW 0x3420 /* 8bit */ 33*2f3f477bSSimon Glass #define DISPBDF 0x3424 /* 16bit */ 34*2f3f477bSSimon Glass #define FD2 0x3428 /* 32bit */ 35*2f3f477bSSimon Glass #define CG 0x341c /* 32bit */ 36*2f3f477bSSimon Glass 37*2f3f477bSSimon Glass /* Function Disable 1 RCBA 0x3418 */ 38*2f3f477bSSimon Glass #define PCH_DISABLE_ALWAYS (1 << 0) 39*2f3f477bSSimon Glass #define PCH_DISABLE_ADSPD (1 << 1) 40*2f3f477bSSimon Glass #define PCH_DISABLE_SATA1 (1 << 2) 41*2f3f477bSSimon Glass #define PCH_DISABLE_SMBUS (1 << 3) 42*2f3f477bSSimon Glass #define PCH_DISABLE_HD_AUDIO (1 << 4) 43*2f3f477bSSimon Glass #define PCH_DISABLE_EHCI2 (1 << 13) 44*2f3f477bSSimon Glass #define PCH_DISABLE_LPC (1 << 14) 45*2f3f477bSSimon Glass #define PCH_DISABLE_EHCI1 (1 << 15) 46*2f3f477bSSimon Glass #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) 47*2f3f477bSSimon Glass #define PCH_DISABLE_THERMAL (1 << 24) 48*2f3f477bSSimon Glass #define PCH_DISABLE_SATA2 (1 << 25) 49*2f3f477bSSimon Glass #define PCH_DISABLE_XHCI (1 << 27) 50*2f3f477bSSimon Glass 51*2f3f477bSSimon Glass /* Function Disable 2 RCBA 0x3428 */ 52*2f3f477bSSimon Glass #define PCH_DISABLE_KT (1 << 4) 53*2f3f477bSSimon Glass #define PCH_DISABLE_IDER (1 << 3) 54*2f3f477bSSimon Glass #define PCH_DISABLE_MEI2 (1 << 2) 55*2f3f477bSSimon Glass #define PCH_DISABLE_MEI1 (1 << 1) 56*2f3f477bSSimon Glass #define PCH_ENABLE_DBDF (1 << 0) 57*2f3f477bSSimon Glass 58*2f3f477bSSimon Glass #endif 59