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Searched refs:PLL1 (Results 1 – 6 of 6) sorted by relevance

/rk3399_rockchip-uboot/board/Barix/ipam390/
H A Dipam390-ais-uart.cfg32 ; This section allows setting up the PLL1. Usually this will
57 ; This section can be used to configure the PLL1 and the EMIF3a registers
155 ; This section allows setting up the PLL1. Usually this will
165 ; This section can be used to configure the PLL1 and the EMIF3a registers
182 ; This section can be used to configure the PLL1 and the EMIF3a registers
/rk3399_rockchip-uboot/doc/
H A DREADME.Heterogeneous-SoCs54 Though there are only 4 PLLs in B4, but in sequence of PLLs from PLL1 -
/rk3399_rockchip-uboot/drivers/video/tegra124/
H A Dsor.c564 DUMP_REG(PLL1); in dump_sor_reg()
723 tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH | in tegra_dc_sor_enable_dp()
H A Dsor.h252 #define PLL1 0x18 macro
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dsun8i-a23-a33.dtsi145 * PLL1 is listed twice here.
H A Dsun6i-a31.dtsi217 * PLL1 is listed twice here.