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Searched refs:PLL0 (Results 1 – 3 of 3) sorted by relevance

/rk3399_rockchip-uboot/drivers/video/tegra124/
H A Dsor.c496 tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */ in tegra_dc_sor_power_up()
516 tegra_sor_write_field(sor, PLL0, in tegra_dc_sor_power_up()
563 DUMP_REG(PLL0); in dump_sor_reg()
710 tegra_sor_writel(sor, PLL0, in tegra_dc_sor_enable_dp()
H A Dsor.h222 #define PLL0 0x17 macro
/rk3399_rockchip-uboot/board/Barix/ipam390/
H A Dipam390-ais-uart.cfg17 ; This section allows setting the PLL0 system clock with a