Searched refs:PCLK (Results 1 – 5 of 5) sorted by relevance
47 #define PCLK (200ul * 1000000ul) macro48 #define BAUDRATE_VAL_M0(bps) (PCLK / (16 * (bps)))49 #define BAUDRATE_VAL_M1(bps) ((bps * (1 << 14)) + (1<<13)) / (PCLK/(1 << 6))
346 0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */
272 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
311 AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
331 FEX files. It can be also set to 0 for selecting PCLK from the