148038c4aSMugunthan V N/* 248038c4aSMugunthan V N * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 348038c4aSMugunthan V N * 448038c4aSMugunthan V N * This program is free software; you can redistribute it and/or modify 548038c4aSMugunthan V N * it under the terms of the GNU General Public License version 2 as 648038c4aSMugunthan V N * published by the Free Software Foundation. 748038c4aSMugunthan V N */ 848038c4aSMugunthan V N 948038c4aSMugunthan V N/* AM437x GP EVM */ 1048038c4aSMugunthan V N 1148038c4aSMugunthan V N/dts-v1/; 1248038c4aSMugunthan V N 1348038c4aSMugunthan V N#include "am4372.dtsi" 1448038c4aSMugunthan V N#include <dt-bindings/pinctrl/am43xx.h> 1548038c4aSMugunthan V N#include <dt-bindings/pwm/pwm.h> 1648038c4aSMugunthan V N#include <dt-bindings/gpio/gpio.h> 1748038c4aSMugunthan V N 1848038c4aSMugunthan V N/ { 1948038c4aSMugunthan V N model = "TI AM437x GP EVM"; 2048038c4aSMugunthan V N compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43"; 2148038c4aSMugunthan V N 2248038c4aSMugunthan V N aliases { 2348038c4aSMugunthan V N display0 = &lcd0; 2448038c4aSMugunthan V N serial3 = &uart3; 2548038c4aSMugunthan V N }; 2648038c4aSMugunthan V N 2748038c4aSMugunthan V N chosen { 2848038c4aSMugunthan V N stdout-path = &uart0; 29ff9e6126SMugunthan V N tick-timer = &timer2; 3048038c4aSMugunthan V N }; 3148038c4aSMugunthan V N 3248038c4aSMugunthan V N vmmcsd_fixed: fixedregulator-sd { 3348038c4aSMugunthan V N compatible = "regulator-fixed"; 3448038c4aSMugunthan V N regulator-name = "vmmcsd_fixed"; 3548038c4aSMugunthan V N regulator-min-microvolt = <3300000>; 3648038c4aSMugunthan V N regulator-max-microvolt = <3300000>; 3748038c4aSMugunthan V N enable-active-high; 3848038c4aSMugunthan V N }; 3948038c4aSMugunthan V N 4048038c4aSMugunthan V N vtt_fixed: fixedregulator-vtt { 4148038c4aSMugunthan V N compatible = "regulator-fixed"; 4248038c4aSMugunthan V N regulator-name = "vtt_fixed"; 4348038c4aSMugunthan V N regulator-min-microvolt = <1500000>; 4448038c4aSMugunthan V N regulator-max-microvolt = <1500000>; 4548038c4aSMugunthan V N regulator-always-on; 4648038c4aSMugunthan V N regulator-boot-on; 4748038c4aSMugunthan V N enable-active-high; 4848038c4aSMugunthan V N gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; 4948038c4aSMugunthan V N }; 5048038c4aSMugunthan V N 5148038c4aSMugunthan V N vmmcwl_fixed: fixedregulator-mmcwl { 5248038c4aSMugunthan V N compatible = "regulator-fixed"; 5348038c4aSMugunthan V N regulator-name = "vmmcwl_fixed"; 5448038c4aSMugunthan V N regulator-min-microvolt = <1800000>; 5548038c4aSMugunthan V N regulator-max-microvolt = <1800000>; 5648038c4aSMugunthan V N gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; 5748038c4aSMugunthan V N enable-active-high; 5848038c4aSMugunthan V N }; 5948038c4aSMugunthan V N 6048038c4aSMugunthan V N backlight { 6148038c4aSMugunthan V N compatible = "pwm-backlight"; 6248038c4aSMugunthan V N pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; 6348038c4aSMugunthan V N brightness-levels = <0 51 53 56 62 75 101 152 255>; 6448038c4aSMugunthan V N default-brightness-level = <8>; 6548038c4aSMugunthan V N }; 6648038c4aSMugunthan V N 6748038c4aSMugunthan V N matrix_keypad: matrix_keypad@0 { 6848038c4aSMugunthan V N compatible = "gpio-matrix-keypad"; 6948038c4aSMugunthan V N debounce-delay-ms = <5>; 7048038c4aSMugunthan V N col-scan-delay-us = <2>; 7148038c4aSMugunthan V N 7248038c4aSMugunthan V N row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */ 7348038c4aSMugunthan V N &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ 7448038c4aSMugunthan V N &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */ 7548038c4aSMugunthan V N 7648038c4aSMugunthan V N col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */ 7748038c4aSMugunthan V N &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */ 7848038c4aSMugunthan V N 7948038c4aSMugunthan V N linux,keymap = <0x00000201 /* P1 */ 8048038c4aSMugunthan V N 0x00010202 /* P2 */ 8148038c4aSMugunthan V N 0x01000067 /* UP */ 8248038c4aSMugunthan V N 0x0101006a /* RIGHT */ 8348038c4aSMugunthan V N 0x02000069 /* LEFT */ 8448038c4aSMugunthan V N 0x0201006c>; /* DOWN */ 8548038c4aSMugunthan V N }; 8648038c4aSMugunthan V N 8748038c4aSMugunthan V N lcd0: display { 8848038c4aSMugunthan V N compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; 8948038c4aSMugunthan V N label = "lcd"; 9048038c4aSMugunthan V N 9148038c4aSMugunthan V N pinctrl-names = "default"; 9248038c4aSMugunthan V N pinctrl-0 = <&lcd_pins>; 9348038c4aSMugunthan V N 9448038c4aSMugunthan V N /* 9548038c4aSMugunthan V N * SelLCDorHDMI, LOW to select HDMI. This is not really the 9648038c4aSMugunthan V N * panel's enable GPIO, but we don't have HDMI driver support nor 9748038c4aSMugunthan V N * support to switch between two displays, so using this gpio as 9848038c4aSMugunthan V N * panel's enable should be safe. 9948038c4aSMugunthan V N */ 10048038c4aSMugunthan V N enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; 10148038c4aSMugunthan V N 10248038c4aSMugunthan V N panel-timing { 10348038c4aSMugunthan V N clock-frequency = <33000000>; 10448038c4aSMugunthan V N hactive = <800>; 10548038c4aSMugunthan V N vactive = <480>; 10648038c4aSMugunthan V N hfront-porch = <210>; 10748038c4aSMugunthan V N hback-porch = <16>; 10848038c4aSMugunthan V N hsync-len = <30>; 10948038c4aSMugunthan V N vback-porch = <10>; 11048038c4aSMugunthan V N vfront-porch = <22>; 11148038c4aSMugunthan V N vsync-len = <13>; 11248038c4aSMugunthan V N hsync-active = <0>; 11348038c4aSMugunthan V N vsync-active = <0>; 11448038c4aSMugunthan V N de-active = <1>; 11548038c4aSMugunthan V N pixelclk-active = <1>; 11648038c4aSMugunthan V N }; 11748038c4aSMugunthan V N 11848038c4aSMugunthan V N port { 11948038c4aSMugunthan V N lcd_in: endpoint { 12048038c4aSMugunthan V N remote-endpoint = <&dpi_out>; 12148038c4aSMugunthan V N }; 12248038c4aSMugunthan V N }; 12348038c4aSMugunthan V N }; 12448038c4aSMugunthan V N 12548038c4aSMugunthan V N /* fixed 12MHz oscillator */ 12648038c4aSMugunthan V N refclk: oscillator { 12748038c4aSMugunthan V N #clock-cells = <0>; 12848038c4aSMugunthan V N compatible = "fixed-clock"; 12948038c4aSMugunthan V N clock-frequency = <12000000>; 13048038c4aSMugunthan V N }; 13148038c4aSMugunthan V N 13248038c4aSMugunthan V N}; 13348038c4aSMugunthan V N 13448038c4aSMugunthan V N&am43xx_pinmux { 13548038c4aSMugunthan V N pinctrl-names = "default", "sleep"; 13648038c4aSMugunthan V N pinctrl-0 = <&wlan_pins_default>; 13748038c4aSMugunthan V N pinctrl-1 = <&wlan_pins_sleep>; 13848038c4aSMugunthan V N 13948038c4aSMugunthan V N i2c0_pins: i2c0_pins { 14048038c4aSMugunthan V N pinctrl-single,pins = < 14148038c4aSMugunthan V N 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 14248038c4aSMugunthan V N 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 14348038c4aSMugunthan V N >; 14448038c4aSMugunthan V N }; 14548038c4aSMugunthan V N 14648038c4aSMugunthan V N i2c1_pins: i2c1_pins { 14748038c4aSMugunthan V N pinctrl-single,pins = < 14848038c4aSMugunthan V N 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ 14948038c4aSMugunthan V N 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ 15048038c4aSMugunthan V N >; 15148038c4aSMugunthan V N }; 15248038c4aSMugunthan V N 15348038c4aSMugunthan V N mmc1_pins: pinmux_mmc1_pins { 15448038c4aSMugunthan V N pinctrl-single,pins = < 15548038c4aSMugunthan V N 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 15648038c4aSMugunthan V N >; 15748038c4aSMugunthan V N }; 15848038c4aSMugunthan V N 15948038c4aSMugunthan V N ecap0_pins: backlight_pins { 16048038c4aSMugunthan V N pinctrl-single,pins = < 16148038c4aSMugunthan V N 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 16248038c4aSMugunthan V N >; 16348038c4aSMugunthan V N }; 16448038c4aSMugunthan V N 16548038c4aSMugunthan V N pixcir_ts_pins: pixcir_ts_pins { 16648038c4aSMugunthan V N pinctrl-single,pins = < 16748038c4aSMugunthan V N 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ 16848038c4aSMugunthan V N >; 16948038c4aSMugunthan V N }; 17048038c4aSMugunthan V N 17148038c4aSMugunthan V N cpsw_default: cpsw_default { 17248038c4aSMugunthan V N pinctrl-single,pins = < 17348038c4aSMugunthan V N /* Slave 1 */ 17448038c4aSMugunthan V N 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ 17548038c4aSMugunthan V N 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ 17648038c4aSMugunthan V N 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ 17748038c4aSMugunthan V N 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ 17848038c4aSMugunthan V N 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ 17948038c4aSMugunthan V N 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ 18048038c4aSMugunthan V N 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ 18148038c4aSMugunthan V N 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ 18248038c4aSMugunthan V N 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ 18348038c4aSMugunthan V N 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ 18448038c4aSMugunthan V N 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ 18548038c4aSMugunthan V N 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ 18648038c4aSMugunthan V N >; 18748038c4aSMugunthan V N }; 18848038c4aSMugunthan V N 18948038c4aSMugunthan V N cpsw_sleep: cpsw_sleep { 19048038c4aSMugunthan V N pinctrl-single,pins = < 19148038c4aSMugunthan V N /* Slave 1 reset value */ 19248038c4aSMugunthan V N 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 19348038c4aSMugunthan V N 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) 19448038c4aSMugunthan V N 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) 19548038c4aSMugunthan V N 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) 19648038c4aSMugunthan V N 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) 19748038c4aSMugunthan V N 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) 19848038c4aSMugunthan V N 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) 19948038c4aSMugunthan V N 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) 20048038c4aSMugunthan V N 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) 20148038c4aSMugunthan V N 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) 20248038c4aSMugunthan V N 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) 20348038c4aSMugunthan V N 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) 20448038c4aSMugunthan V N >; 20548038c4aSMugunthan V N }; 20648038c4aSMugunthan V N 20748038c4aSMugunthan V N davinci_mdio_default: davinci_mdio_default { 20848038c4aSMugunthan V N pinctrl-single,pins = < 20948038c4aSMugunthan V N /* MDIO */ 21048038c4aSMugunthan V N 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 21148038c4aSMugunthan V N 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 21248038c4aSMugunthan V N >; 21348038c4aSMugunthan V N }; 21448038c4aSMugunthan V N 21548038c4aSMugunthan V N davinci_mdio_sleep: davinci_mdio_sleep { 21648038c4aSMugunthan V N pinctrl-single,pins = < 21748038c4aSMugunthan V N /* MDIO reset value */ 21848038c4aSMugunthan V N 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) 21948038c4aSMugunthan V N 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 22048038c4aSMugunthan V N >; 22148038c4aSMugunthan V N }; 22248038c4aSMugunthan V N 22348038c4aSMugunthan V N nand_flash_x8: nand_flash_x8 { 22448038c4aSMugunthan V N pinctrl-single,pins = < 22548038c4aSMugunthan V N 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */ 22648038c4aSMugunthan V N 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 22748038c4aSMugunthan V N 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 22848038c4aSMugunthan V N 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 22948038c4aSMugunthan V N 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 23048038c4aSMugunthan V N 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 23148038c4aSMugunthan V N 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 23248038c4aSMugunthan V N 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 23348038c4aSMugunthan V N 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 23448038c4aSMugunthan V N 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 23548038c4aSMugunthan V N 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ 23648038c4aSMugunthan V N 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 23748038c4aSMugunthan V N 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 23848038c4aSMugunthan V N 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 23948038c4aSMugunthan V N 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 24048038c4aSMugunthan V N 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 24148038c4aSMugunthan V N >; 24248038c4aSMugunthan V N }; 24348038c4aSMugunthan V N 24448038c4aSMugunthan V N dss_pins: dss_pins { 24548038c4aSMugunthan V N pinctrl-single,pins = < 24648038c4aSMugunthan V N 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ 24748038c4aSMugunthan V N 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1) 24848038c4aSMugunthan V N 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1) 24948038c4aSMugunthan V N 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1) 25048038c4aSMugunthan V N 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1) 25148038c4aSMugunthan V N 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1) 25248038c4aSMugunthan V N 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1) 25348038c4aSMugunthan V N 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ 25448038c4aSMugunthan V N 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ 25548038c4aSMugunthan V N 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 25648038c4aSMugunthan V N 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 25748038c4aSMugunthan V N 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0) 25848038c4aSMugunthan V N 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 25948038c4aSMugunthan V N 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 26048038c4aSMugunthan V N 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 26148038c4aSMugunthan V N 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0) 26248038c4aSMugunthan V N 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 26348038c4aSMugunthan V N 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 26448038c4aSMugunthan V N 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 26548038c4aSMugunthan V N 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0) 26648038c4aSMugunthan V N 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 26748038c4aSMugunthan V N 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 26848038c4aSMugunthan V N 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 26948038c4aSMugunthan V N 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ 27048038c4aSMugunthan V N 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ 27148038c4aSMugunthan V N 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ 27248038c4aSMugunthan V N 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ 27348038c4aSMugunthan V N 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ 27448038c4aSMugunthan V N 27548038c4aSMugunthan V N >; 27648038c4aSMugunthan V N }; 27748038c4aSMugunthan V N 27848038c4aSMugunthan V N lcd_pins: lcd_pins { 27948038c4aSMugunthan V N pinctrl-single,pins = < 28048038c4aSMugunthan V N /* GPIO 5_8 to select LCD / HDMI */ 28148038c4aSMugunthan V N 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) 28248038c4aSMugunthan V N >; 28348038c4aSMugunthan V N }; 28448038c4aSMugunthan V N 28548038c4aSMugunthan V N dcan0_default: dcan0_default_pins { 28648038c4aSMugunthan V N pinctrl-single,pins = < 28748038c4aSMugunthan V N 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ 28848038c4aSMugunthan V N 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ 28948038c4aSMugunthan V N >; 29048038c4aSMugunthan V N }; 29148038c4aSMugunthan V N 29248038c4aSMugunthan V N dcan1_default: dcan1_default_pins { 29348038c4aSMugunthan V N pinctrl-single,pins = < 29448038c4aSMugunthan V N 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ 29548038c4aSMugunthan V N 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ 29648038c4aSMugunthan V N >; 29748038c4aSMugunthan V N }; 29848038c4aSMugunthan V N 29948038c4aSMugunthan V N vpfe0_pins_default: vpfe0_pins_default { 30048038c4aSMugunthan V N pinctrl-single,pins = < 30148038c4aSMugunthan V N 0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ 30248038c4aSMugunthan V N 0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ 30348038c4aSMugunthan V N 0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ 30448038c4aSMugunthan V N 0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ 30548038c4aSMugunthan V N 0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ 30648038c4aSMugunthan V N 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ 30748038c4aSMugunthan V N 0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ 30848038c4aSMugunthan V N 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ 30948038c4aSMugunthan V N 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ 31048038c4aSMugunthan V N 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ 31148038c4aSMugunthan V N 0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ 31248038c4aSMugunthan V N 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ 31348038c4aSMugunthan V N 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ 31448038c4aSMugunthan V N >; 31548038c4aSMugunthan V N }; 31648038c4aSMugunthan V N 31748038c4aSMugunthan V N vpfe0_pins_sleep: vpfe0_pins_sleep { 31848038c4aSMugunthan V N pinctrl-single,pins = < 31948038c4aSMugunthan V N 0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/ 32048038c4aSMugunthan V N 0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/ 32148038c4aSMugunthan V N 0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/ 32248038c4aSMugunthan V N 0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/ 32348038c4aSMugunthan V N 0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/ 32448038c4aSMugunthan V N 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/ 32548038c4aSMugunthan V N 0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/ 32648038c4aSMugunthan V N 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/ 32748038c4aSMugunthan V N 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/ 32848038c4aSMugunthan V N 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/ 32948038c4aSMugunthan V N 0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/ 33048038c4aSMugunthan V N 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/ 33148038c4aSMugunthan V N 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/ 33248038c4aSMugunthan V N >; 33348038c4aSMugunthan V N }; 33448038c4aSMugunthan V N 33548038c4aSMugunthan V N vpfe1_pins_default: vpfe1_pins_default { 33648038c4aSMugunthan V N pinctrl-single,pins = < 33748038c4aSMugunthan V N 0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/ 33848038c4aSMugunthan V N 0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/ 33948038c4aSMugunthan V N 0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/ 34048038c4aSMugunthan V N 0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/ 34148038c4aSMugunthan V N 0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/ 34248038c4aSMugunthan V N 0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/ 34348038c4aSMugunthan V N 0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/ 34448038c4aSMugunthan V N 0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/ 34548038c4aSMugunthan V N 0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/ 34648038c4aSMugunthan V N 0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/ 34748038c4aSMugunthan V N 0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/ 34848038c4aSMugunthan V N 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/ 34948038c4aSMugunthan V N 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/ 35048038c4aSMugunthan V N >; 35148038c4aSMugunthan V N }; 35248038c4aSMugunthan V N 35348038c4aSMugunthan V N vpfe1_pins_sleep: vpfe1_pins_sleep { 35448038c4aSMugunthan V N pinctrl-single,pins = < 35548038c4aSMugunthan V N 0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/ 35648038c4aSMugunthan V N 0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/ 35748038c4aSMugunthan V N 0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/ 35848038c4aSMugunthan V N 0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/ 35948038c4aSMugunthan V N 0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/ 36048038c4aSMugunthan V N 0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/ 36148038c4aSMugunthan V N 0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/ 36248038c4aSMugunthan V N 0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/ 36348038c4aSMugunthan V N 0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/ 36448038c4aSMugunthan V N 0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/ 36548038c4aSMugunthan V N 0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/ 36648038c4aSMugunthan V N 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/ 36748038c4aSMugunthan V N 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/ 36848038c4aSMugunthan V N >; 36948038c4aSMugunthan V N }; 37048038c4aSMugunthan V N 37148038c4aSMugunthan V N mmc3_pins_default: pinmux_mmc3_pins_default { 37248038c4aSMugunthan V N pinctrl-single,pins = < 37348038c4aSMugunthan V N 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ 37448038c4aSMugunthan V N 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ 37548038c4aSMugunthan V N 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ 37648038c4aSMugunthan V N 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ 37748038c4aSMugunthan V N 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ 37848038c4aSMugunthan V N 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */ 37948038c4aSMugunthan V N >; 38048038c4aSMugunthan V N }; 38148038c4aSMugunthan V N 38248038c4aSMugunthan V N mmc3_pins_sleep: pinmux_mmc3_pins_sleep { 38348038c4aSMugunthan V N pinctrl-single,pins = < 38448038c4aSMugunthan V N 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ 38548038c4aSMugunthan V N 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ 38648038c4aSMugunthan V N 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */ 38748038c4aSMugunthan V N 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */ 38848038c4aSMugunthan V N 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */ 38948038c4aSMugunthan V N 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */ 39048038c4aSMugunthan V N >; 39148038c4aSMugunthan V N }; 39248038c4aSMugunthan V N 39348038c4aSMugunthan V N wlan_pins_default: pinmux_wlan_pins_default { 39448038c4aSMugunthan V N pinctrl-single,pins = < 39548038c4aSMugunthan V N 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ 39648038c4aSMugunthan V N 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ 39748038c4aSMugunthan V N 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ 39848038c4aSMugunthan V N >; 39948038c4aSMugunthan V N }; 40048038c4aSMugunthan V N 40148038c4aSMugunthan V N wlan_pins_sleep: pinmux_wlan_pins_sleep { 40248038c4aSMugunthan V N pinctrl-single,pins = < 40348038c4aSMugunthan V N 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ 40448038c4aSMugunthan V N 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ 40548038c4aSMugunthan V N 0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ 40648038c4aSMugunthan V N >; 40748038c4aSMugunthan V N }; 40848038c4aSMugunthan V N 40948038c4aSMugunthan V N uart3_pins: uart3_pins { 41048038c4aSMugunthan V N pinctrl-single,pins = < 41148038c4aSMugunthan V N 0x228 (PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ 41248038c4aSMugunthan V N 0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ 41348038c4aSMugunthan V N 0x230 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */ 41448038c4aSMugunthan V N 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ 41548038c4aSMugunthan V N >; 41648038c4aSMugunthan V N }; 41748038c4aSMugunthan V N}; 41848038c4aSMugunthan V N 41948038c4aSMugunthan V N&i2c0 { 42048038c4aSMugunthan V N status = "okay"; 42148038c4aSMugunthan V N pinctrl-names = "default"; 42248038c4aSMugunthan V N pinctrl-0 = <&i2c0_pins>; 42348038c4aSMugunthan V N clock-frequency = <100000>; 42448038c4aSMugunthan V N 42548038c4aSMugunthan V N tps65218: tps65218@24 { 42648038c4aSMugunthan V N reg = <0x24>; 42748038c4aSMugunthan V N compatible = "ti,tps65218"; 42848038c4aSMugunthan V N interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ 42948038c4aSMugunthan V N interrupt-controller; 43048038c4aSMugunthan V N #interrupt-cells = <2>; 43148038c4aSMugunthan V N 43248038c4aSMugunthan V N dcdc1: regulator-dcdc1 { 43348038c4aSMugunthan V N compatible = "ti,tps65218-dcdc1"; 43448038c4aSMugunthan V N regulator-name = "vdd_core"; 43548038c4aSMugunthan V N regulator-min-microvolt = <912000>; 43648038c4aSMugunthan V N regulator-max-microvolt = <1144000>; 43748038c4aSMugunthan V N regulator-boot-on; 43848038c4aSMugunthan V N regulator-always-on; 43948038c4aSMugunthan V N }; 44048038c4aSMugunthan V N 44148038c4aSMugunthan V N dcdc2: regulator-dcdc2 { 44248038c4aSMugunthan V N compatible = "ti,tps65218-dcdc2"; 44348038c4aSMugunthan V N regulator-name = "vdd_mpu"; 44448038c4aSMugunthan V N regulator-min-microvolt = <912000>; 44548038c4aSMugunthan V N regulator-max-microvolt = <1378000>; 44648038c4aSMugunthan V N regulator-boot-on; 44748038c4aSMugunthan V N regulator-always-on; 44848038c4aSMugunthan V N }; 44948038c4aSMugunthan V N 45048038c4aSMugunthan V N dcdc3: regulator-dcdc3 { 45148038c4aSMugunthan V N compatible = "ti,tps65218-dcdc3"; 45248038c4aSMugunthan V N regulator-name = "vdcdc3"; 45348038c4aSMugunthan V N regulator-min-microvolt = <1500000>; 45448038c4aSMugunthan V N regulator-max-microvolt = <1500000>; 45548038c4aSMugunthan V N regulator-boot-on; 45648038c4aSMugunthan V N regulator-always-on; 45748038c4aSMugunthan V N }; 45848038c4aSMugunthan V N dcdc5: regulator-dcdc5 { 45948038c4aSMugunthan V N compatible = "ti,tps65218-dcdc5"; 46048038c4aSMugunthan V N regulator-name = "v1_0bat"; 46148038c4aSMugunthan V N regulator-min-microvolt = <1000000>; 46248038c4aSMugunthan V N regulator-max-microvolt = <1000000>; 46348038c4aSMugunthan V N }; 46448038c4aSMugunthan V N 46548038c4aSMugunthan V N dcdc6: regulator-dcdc6 { 46648038c4aSMugunthan V N compatible = "ti,tps65218-dcdc6"; 46748038c4aSMugunthan V N regulator-name = "v1_8bat"; 46848038c4aSMugunthan V N regulator-min-microvolt = <1800000>; 46948038c4aSMugunthan V N regulator-max-microvolt = <1800000>; 47048038c4aSMugunthan V N }; 47148038c4aSMugunthan V N 47248038c4aSMugunthan V N ldo1: regulator-ldo1 { 47348038c4aSMugunthan V N compatible = "ti,tps65218-ldo1"; 47448038c4aSMugunthan V N regulator-min-microvolt = <1800000>; 47548038c4aSMugunthan V N regulator-max-microvolt = <1800000>; 47648038c4aSMugunthan V N regulator-boot-on; 47748038c4aSMugunthan V N regulator-always-on; 47848038c4aSMugunthan V N }; 47948038c4aSMugunthan V N }; 48048038c4aSMugunthan V N 48148038c4aSMugunthan V N ov2659@30 { 48248038c4aSMugunthan V N compatible = "ovti,ov2659"; 48348038c4aSMugunthan V N reg = <0x30>; 48448038c4aSMugunthan V N 48548038c4aSMugunthan V N clocks = <&refclk 0>; 48648038c4aSMugunthan V N clock-names = "xvclk"; 48748038c4aSMugunthan V N 48848038c4aSMugunthan V N port { 48948038c4aSMugunthan V N ov2659_0: endpoint { 49048038c4aSMugunthan V N remote-endpoint = <&vpfe1_ep>; 49148038c4aSMugunthan V N link-frequencies = /bits/ 64 <70000000>; 49248038c4aSMugunthan V N }; 49348038c4aSMugunthan V N }; 49448038c4aSMugunthan V N }; 49548038c4aSMugunthan V N}; 49648038c4aSMugunthan V N 49748038c4aSMugunthan V N&i2c1 { 49848038c4aSMugunthan V N status = "okay"; 49948038c4aSMugunthan V N pinctrl-names = "default"; 50048038c4aSMugunthan V N pinctrl-0 = <&i2c1_pins>; 50148038c4aSMugunthan V N pixcir_ts@5c { 50248038c4aSMugunthan V N compatible = "pixcir,pixcir_tangoc"; 50348038c4aSMugunthan V N pinctrl-names = "default"; 50448038c4aSMugunthan V N pinctrl-0 = <&pixcir_ts_pins>; 50548038c4aSMugunthan V N reg = <0x5c>; 50648038c4aSMugunthan V N interrupt-parent = <&gpio3>; 50748038c4aSMugunthan V N interrupts = <22 0>; 50848038c4aSMugunthan V N 50948038c4aSMugunthan V N attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 51048038c4aSMugunthan V N 51148038c4aSMugunthan V N touchscreen-size-x = <1024>; 51248038c4aSMugunthan V N touchscreen-size-y = <600>; 51348038c4aSMugunthan V N }; 51448038c4aSMugunthan V N 51548038c4aSMugunthan V N ov2659@30 { 51648038c4aSMugunthan V N compatible = "ovti,ov2659"; 51748038c4aSMugunthan V N reg = <0x30>; 51848038c4aSMugunthan V N 51948038c4aSMugunthan V N clocks = <&refclk 0>; 52048038c4aSMugunthan V N clock-names = "xvclk"; 52148038c4aSMugunthan V N 52248038c4aSMugunthan V N port { 52348038c4aSMugunthan V N ov2659_1: endpoint { 52448038c4aSMugunthan V N remote-endpoint = <&vpfe0_ep>; 52548038c4aSMugunthan V N link-frequencies = /bits/ 64 <70000000>; 52648038c4aSMugunthan V N }; 52748038c4aSMugunthan V N }; 52848038c4aSMugunthan V N }; 52948038c4aSMugunthan V N}; 53048038c4aSMugunthan V N 53148038c4aSMugunthan V N&epwmss0 { 53248038c4aSMugunthan V N status = "okay"; 53348038c4aSMugunthan V N}; 53448038c4aSMugunthan V N 53548038c4aSMugunthan V N&tscadc { 53648038c4aSMugunthan V N status = "okay"; 53748038c4aSMugunthan V N 53848038c4aSMugunthan V N adc { 53948038c4aSMugunthan V N ti,adc-channels = <0 1 2 3 4 5 6 7>; 54048038c4aSMugunthan V N }; 54148038c4aSMugunthan V N}; 54248038c4aSMugunthan V N 54348038c4aSMugunthan V N&ecap0 { 54448038c4aSMugunthan V N status = "okay"; 54548038c4aSMugunthan V N pinctrl-names = "default"; 54648038c4aSMugunthan V N pinctrl-0 = <&ecap0_pins>; 54748038c4aSMugunthan V N}; 54848038c4aSMugunthan V N 54948038c4aSMugunthan V N&gpio0 { 55048038c4aSMugunthan V N status = "okay"; 55148038c4aSMugunthan V N}; 55248038c4aSMugunthan V N 55348038c4aSMugunthan V N&gpio1 { 55448038c4aSMugunthan V N status = "okay"; 55548038c4aSMugunthan V N}; 55648038c4aSMugunthan V N 55748038c4aSMugunthan V N&gpio3 { 55848038c4aSMugunthan V N status = "okay"; 55948038c4aSMugunthan V N}; 56048038c4aSMugunthan V N 56148038c4aSMugunthan V N&gpio4 { 56248038c4aSMugunthan V N status = "okay"; 56348038c4aSMugunthan V N}; 56448038c4aSMugunthan V N 56548038c4aSMugunthan V N&gpio5 { 56648038c4aSMugunthan V N status = "okay"; 56748038c4aSMugunthan V N ti,no-reset-on-init; 56848038c4aSMugunthan V N}; 56948038c4aSMugunthan V N 57048038c4aSMugunthan V N&mmc1 { 57148038c4aSMugunthan V N status = "okay"; 57248038c4aSMugunthan V N vmmc-supply = <&vmmcsd_fixed>; 57348038c4aSMugunthan V N bus-width = <4>; 57448038c4aSMugunthan V N pinctrl-names = "default"; 57548038c4aSMugunthan V N pinctrl-0 = <&mmc1_pins>; 576*103afa2aSMugunthan V N cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 57748038c4aSMugunthan V N}; 57848038c4aSMugunthan V N 57948038c4aSMugunthan V N&mmc3 { 58048038c4aSMugunthan V N /* disable MMC3 as SDIO is not supported in U-Boot */ 58148038c4aSMugunthan V N status = "disabled"; 58248038c4aSMugunthan V N /* these are on the crossbar and are outlined in the 58348038c4aSMugunthan V N xbar-event-map element */ 58448038c4aSMugunthan V N dmas = <&edma 30 58548038c4aSMugunthan V N &edma 31>; 58648038c4aSMugunthan V N dma-names = "tx", "rx"; 58748038c4aSMugunthan V N vmmc-supply = <&vmmcwl_fixed>; 58848038c4aSMugunthan V N bus-width = <4>; 58948038c4aSMugunthan V N pinctrl-names = "default", "sleep"; 59048038c4aSMugunthan V N pinctrl-0 = <&mmc3_pins_default>; 59148038c4aSMugunthan V N pinctrl-1 = <&mmc3_pins_sleep>; 59248038c4aSMugunthan V N cap-power-off-card; 59348038c4aSMugunthan V N keep-power-in-suspend; 59448038c4aSMugunthan V N ti,non-removable; 59548038c4aSMugunthan V N 59648038c4aSMugunthan V N #address-cells = <1>; 59748038c4aSMugunthan V N #size-cells = <0>; 59848038c4aSMugunthan V N wlcore: wlcore@0 { 59948038c4aSMugunthan V N compatible = "ti,wl1835"; 60048038c4aSMugunthan V N reg = <2>; 60148038c4aSMugunthan V N interrupt-parent = <&gpio1>; 60248038c4aSMugunthan V N interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 60348038c4aSMugunthan V N }; 60448038c4aSMugunthan V N}; 60548038c4aSMugunthan V N 60648038c4aSMugunthan V N&edma { 60748038c4aSMugunthan V N ti,edma-xbar-event-map = /bits/ 16 <1 30 60848038c4aSMugunthan V N 2 31>; 60948038c4aSMugunthan V N}; 61048038c4aSMugunthan V N 61148038c4aSMugunthan V N&uart3 { 61248038c4aSMugunthan V N status = "okay"; 61348038c4aSMugunthan V N pinctrl-names = "default"; 61448038c4aSMugunthan V N pinctrl-0 = <&uart3_pins>; 61548038c4aSMugunthan V N}; 61648038c4aSMugunthan V N 61748038c4aSMugunthan V N&usb2_phy1 { 61848038c4aSMugunthan V N status = "okay"; 61948038c4aSMugunthan V N}; 62048038c4aSMugunthan V N 62148038c4aSMugunthan V N&usb1 { 62248038c4aSMugunthan V N dr_mode = "peripheral"; 62348038c4aSMugunthan V N status = "okay"; 62448038c4aSMugunthan V N}; 62548038c4aSMugunthan V N 62648038c4aSMugunthan V N&usb2_phy2 { 62748038c4aSMugunthan V N status = "okay"; 62848038c4aSMugunthan V N}; 62948038c4aSMugunthan V N 63048038c4aSMugunthan V N&usb2 { 63148038c4aSMugunthan V N dr_mode = "host"; 63248038c4aSMugunthan V N status = "okay"; 63348038c4aSMugunthan V N}; 63448038c4aSMugunthan V N 63548038c4aSMugunthan V N&mac { 63648038c4aSMugunthan V N slaves = <1>; 63748038c4aSMugunthan V N pinctrl-names = "default", "sleep"; 63848038c4aSMugunthan V N pinctrl-0 = <&cpsw_default>; 63948038c4aSMugunthan V N pinctrl-1 = <&cpsw_sleep>; 64048038c4aSMugunthan V N status = "okay"; 64148038c4aSMugunthan V N}; 64248038c4aSMugunthan V N 64348038c4aSMugunthan V N&davinci_mdio { 64448038c4aSMugunthan V N pinctrl-names = "default", "sleep"; 64548038c4aSMugunthan V N pinctrl-0 = <&davinci_mdio_default>; 64648038c4aSMugunthan V N pinctrl-1 = <&davinci_mdio_sleep>; 64748038c4aSMugunthan V N status = "okay"; 64848038c4aSMugunthan V N}; 64948038c4aSMugunthan V N 65048038c4aSMugunthan V N&cpsw_emac0 { 65148038c4aSMugunthan V N phy_id = <&davinci_mdio>, <0>; 65248038c4aSMugunthan V N phy-mode = "rgmii"; 65348038c4aSMugunthan V N}; 65448038c4aSMugunthan V N 65548038c4aSMugunthan V N&elm { 65648038c4aSMugunthan V N status = "okay"; 65748038c4aSMugunthan V N}; 65848038c4aSMugunthan V N 65948038c4aSMugunthan V N&gpmc { 66048038c4aSMugunthan V N status = "okay"; 66148038c4aSMugunthan V N pinctrl-names = "default"; 66248038c4aSMugunthan V N pinctrl-0 = <&nand_flash_x8>; 66348038c4aSMugunthan V N ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ 66448038c4aSMugunthan V N nand@0,0 { 66548038c4aSMugunthan V N reg = <0 0 4>; /* device IO registers */ 66648038c4aSMugunthan V N ti,nand-ecc-opt = "bch16"; 66748038c4aSMugunthan V N ti,elm-id = <&elm>; 66848038c4aSMugunthan V N nand-bus-width = <8>; 66948038c4aSMugunthan V N gpmc,device-width = <1>; 67048038c4aSMugunthan V N gpmc,sync-clk-ps = <0>; 67148038c4aSMugunthan V N gpmc,cs-on-ns = <0>; 67248038c4aSMugunthan V N gpmc,cs-rd-off-ns = <40>; 67348038c4aSMugunthan V N gpmc,cs-wr-off-ns = <40>; 67448038c4aSMugunthan V N gpmc,adv-on-ns = <0>; 67548038c4aSMugunthan V N gpmc,adv-rd-off-ns = <25>; 67648038c4aSMugunthan V N gpmc,adv-wr-off-ns = <25>; 67748038c4aSMugunthan V N gpmc,we-on-ns = <0>; 67848038c4aSMugunthan V N gpmc,we-off-ns = <20>; 67948038c4aSMugunthan V N gpmc,oe-on-ns = <3>; 68048038c4aSMugunthan V N gpmc,oe-off-ns = <30>; 68148038c4aSMugunthan V N gpmc,access-ns = <30>; 68248038c4aSMugunthan V N gpmc,rd-cycle-ns = <40>; 68348038c4aSMugunthan V N gpmc,wr-cycle-ns = <40>; 68448038c4aSMugunthan V N gpmc,wait-pin = <0>; 68548038c4aSMugunthan V N gpmc,bus-turnaround-ns = <0>; 68648038c4aSMugunthan V N gpmc,cycle2cycle-delay-ns = <0>; 68748038c4aSMugunthan V N gpmc,clk-activation-ns = <0>; 68848038c4aSMugunthan V N gpmc,wait-monitoring-ns = <0>; 68948038c4aSMugunthan V N gpmc,wr-access-ns = <40>; 69048038c4aSMugunthan V N gpmc,wr-data-mux-bus-ns = <0>; 69148038c4aSMugunthan V N /* MTD partition table */ 69248038c4aSMugunthan V N /* All SPL-* partitions are sized to minimal length 69348038c4aSMugunthan V N * which can be independently programmable. For 69448038c4aSMugunthan V N * NAND flash this is equal to size of erase-block */ 69548038c4aSMugunthan V N #address-cells = <1>; 69648038c4aSMugunthan V N #size-cells = <1>; 69748038c4aSMugunthan V N partition@0 { 69848038c4aSMugunthan V N label = "NAND.SPL"; 69948038c4aSMugunthan V N reg = <0x00000000 0x00040000>; 70048038c4aSMugunthan V N }; 70148038c4aSMugunthan V N partition@1 { 70248038c4aSMugunthan V N label = "NAND.SPL.backup1"; 70348038c4aSMugunthan V N reg = <0x00040000 0x00040000>; 70448038c4aSMugunthan V N }; 70548038c4aSMugunthan V N partition@2 { 70648038c4aSMugunthan V N label = "NAND.SPL.backup2"; 70748038c4aSMugunthan V N reg = <0x00080000 0x00040000>; 70848038c4aSMugunthan V N }; 70948038c4aSMugunthan V N partition@3 { 71048038c4aSMugunthan V N label = "NAND.SPL.backup3"; 71148038c4aSMugunthan V N reg = <0x000c0000 0x00040000>; 71248038c4aSMugunthan V N }; 71348038c4aSMugunthan V N partition@4 { 71448038c4aSMugunthan V N label = "NAND.u-boot-spl-os"; 71548038c4aSMugunthan V N reg = <0x00100000 0x00080000>; 71648038c4aSMugunthan V N }; 71748038c4aSMugunthan V N partition@5 { 71848038c4aSMugunthan V N label = "NAND.u-boot"; 71948038c4aSMugunthan V N reg = <0x00180000 0x00100000>; 72048038c4aSMugunthan V N }; 72148038c4aSMugunthan V N partition@6 { 72248038c4aSMugunthan V N label = "NAND.u-boot-env"; 72348038c4aSMugunthan V N reg = <0x00280000 0x00040000>; 72448038c4aSMugunthan V N }; 72548038c4aSMugunthan V N partition@7 { 72648038c4aSMugunthan V N label = "NAND.u-boot-env.backup1"; 72748038c4aSMugunthan V N reg = <0x002c0000 0x00040000>; 72848038c4aSMugunthan V N }; 72948038c4aSMugunthan V N partition@8 { 73048038c4aSMugunthan V N label = "NAND.kernel"; 73148038c4aSMugunthan V N reg = <0x00300000 0x00700000>; 73248038c4aSMugunthan V N }; 73348038c4aSMugunthan V N partition@9 { 73448038c4aSMugunthan V N label = "NAND.file-system"; 73548038c4aSMugunthan V N reg = <0x00a00000 0x1f600000>; 73648038c4aSMugunthan V N }; 73748038c4aSMugunthan V N }; 73848038c4aSMugunthan V N}; 73948038c4aSMugunthan V N 74048038c4aSMugunthan V N&dss { 74148038c4aSMugunthan V N status = "ok"; 74248038c4aSMugunthan V N 74348038c4aSMugunthan V N pinctrl-names = "default"; 74448038c4aSMugunthan V N pinctrl-0 = <&dss_pins>; 74548038c4aSMugunthan V N 74648038c4aSMugunthan V N port { 74748038c4aSMugunthan V N dpi_out: endpoint@0 { 74848038c4aSMugunthan V N remote-endpoint = <&lcd_in>; 74948038c4aSMugunthan V N data-lines = <24>; 75048038c4aSMugunthan V N }; 75148038c4aSMugunthan V N }; 75248038c4aSMugunthan V N}; 75348038c4aSMugunthan V N 75448038c4aSMugunthan V N&dcan0 { 75548038c4aSMugunthan V N pinctrl-names = "default"; 75648038c4aSMugunthan V N pinctrl-0 = <&dcan0_default>; 75748038c4aSMugunthan V N status = "okay"; 75848038c4aSMugunthan V N}; 75948038c4aSMugunthan V N 76048038c4aSMugunthan V N&dcan1 { 76148038c4aSMugunthan V N pinctrl-names = "default"; 76248038c4aSMugunthan V N pinctrl-0 = <&dcan1_default>; 76348038c4aSMugunthan V N status = "okay"; 76448038c4aSMugunthan V N}; 76548038c4aSMugunthan V N 76648038c4aSMugunthan V N&vpfe0 { 76748038c4aSMugunthan V N status = "okay"; 76848038c4aSMugunthan V N pinctrl-names = "default", "sleep"; 76948038c4aSMugunthan V N pinctrl-0 = <&vpfe0_pins_default>; 77048038c4aSMugunthan V N pinctrl-1 = <&vpfe0_pins_sleep>; 77148038c4aSMugunthan V N 77248038c4aSMugunthan V N port { 77348038c4aSMugunthan V N vpfe0_ep: endpoint { 77448038c4aSMugunthan V N remote-endpoint = <&ov2659_1>; 77548038c4aSMugunthan V N ti,am437x-vpfe-interface = <0>; 77648038c4aSMugunthan V N bus-width = <8>; 77748038c4aSMugunthan V N hsync-active = <0>; 77848038c4aSMugunthan V N vsync-active = <0>; 77948038c4aSMugunthan V N }; 78048038c4aSMugunthan V N }; 78148038c4aSMugunthan V N}; 78248038c4aSMugunthan V N 78348038c4aSMugunthan V N&vpfe1 { 78448038c4aSMugunthan V N status = "okay"; 78548038c4aSMugunthan V N pinctrl-names = "default", "sleep"; 78648038c4aSMugunthan V N pinctrl-0 = <&vpfe1_pins_default>; 78748038c4aSMugunthan V N pinctrl-1 = <&vpfe1_pins_sleep>; 78848038c4aSMugunthan V N 78948038c4aSMugunthan V N port { 79048038c4aSMugunthan V N vpfe1_ep: endpoint { 79148038c4aSMugunthan V N remote-endpoint = <&ov2659_0>; 79248038c4aSMugunthan V N ti,am437x-vpfe-interface = <0>; 79348038c4aSMugunthan V N bus-width = <8>; 79448038c4aSMugunthan V N hsync-active = <0>; 79548038c4aSMugunthan V N vsync-active = <0>; 79648038c4aSMugunthan V N }; 79748038c4aSMugunthan V N }; 79848038c4aSMugunthan V N}; 799