Searched refs:MCFSIM_DACR0 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_rockchip-uboot/board/freescale/m5253evbe/ |
| H A D | m5253evbe.c | 40 mbar_writeLong(MCFSIM_DACR0, 0x00002320); in dram_init()
48 mbar_writeLong(MCFSIM_DACR0, 0x00002328); in dram_init()
56 mbar_writeLong(MCFSIM_DACR0, in dram_init()
57 mbar_readLong(MCFSIM_DACR0) | 0x8000); in dram_init()
64 mbar_writeLong(MCFSIM_DACR0, in dram_init()
65 mbar_readLong(MCFSIM_DACR0) | 0x0040); in dram_init()
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| /rk3399_rockchip-uboot/board/freescale/m5253demo/ |
| H A D | m5253demo.c | 43 mbar_writeLong(MCFSIM_DACR0, 0x00003224); in dram_init()
52 mbar_writeLong(MCFSIM_DACR0, 0x0000322c); in dram_init()
62 mbar_writeLong(MCFSIM_DACR0, in dram_init()
63 mbar_readLong(MCFSIM_DACR0) | 0x8000); in dram_init()
70 mbar_writeLong(MCFSIM_DACR0, in dram_init()
71 mbar_readLong(MCFSIM_DACR0) | 0x0040); in dram_init()
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| /rk3399_rockchip-uboot/board/freescale/m5249evb/ |
| H A D | m5249evb.c | 69 mbar_writeLong(MCFSIM_DACR0, 0x00003324); in dram_init()
75 mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ in dram_init()
80 mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ in dram_init()
84 mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ in dram_init()
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| /rk3399_rockchip-uboot/arch/m68k/include/asm/ |
| H A D | m5249.h | 65 #define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ macro
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