Searched refs:MAX_DELAY (Results 1 – 5 of 5) sorted by relevance
522 ui_max_delay = MAX_DELAY; in ddr3_read_leveling_single_cs_rl_mode()944 ui_max_delay = MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()1134 MAX_DELAY + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()1136 MAX_DELAY + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()1139 phase = tmp / MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()1145 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()1155 delay_s = dram_info->rl_val[cs][idx][PS] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()1157 delay_e = dram_info->rl_val[cs][idx][PE] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()1161 phase = tmp / MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()1169 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
124 #define MAX_DELAY 0x1F macro
1223 for (delay = 0; delay < MAX_DELAY; delay++) { in ddr3_write_leveling_single_cs()1294 delay = MAX_DELAY; in ddr3_write_leveling_single_cs()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail()960 MAX_DELAY); in ddr3_rx_shift_dqs_to_first_fail()
917 && (centralization_high_limit[pup] == MAX_DELAY)) in ddr3_center_calc()