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Searched refs:M7 (Results 1 – 17 of 17) sorted by relevance

/rk3399_rockchip-uboot/board/amazon/kc1/
H A Dkc1.h34 { CAM_SHUTTER, (IDIS | DIS | M7) }, /* safe_mode */
35 { CAM_STROBE, (IDIS | DIS | M7) }, /* safe_mode */
36 { CAM_GLOBALRESET, (IDIS | DIS | M7) }, /* safe_mode */
38 { HDQ_SIO, (IDIS | DIS | M7) }, /* safe_mode */
52 { MCSPI1_CLK, (IDIS | DIS | M7) }, /* safe_mode */
53 { MCSPI1_SOMI, (IDIS | DIS | M7) }, /* safe_mode */
54 { MCSPI1_SIMO, (IDIS | DIS | M7) }, /* safe_mode */
55 { MCSPI1_CS0, (IDIS | DIS | M7) }, /* safe_mode */
56 { MCSPI1_CS1, (IDIS | DIS | M7) }, /* safe_mode */
57 { MCSPI1_CS2, (IDIS | DIS | M7) }, /* safe_mode */
[all …]
/rk3399_rockchip-uboot/board/quipos/cairo/
H A Dcairo.h29 MUX_VAL(CONTROL_PADCONF_GPIO112, (IEN | PTD | EN | M7)) \
30 MUX_VAL(CONTROL_PADCONF_GPIO113, (IEN | PTD | EN | M7)) \
31 MUX_VAL(CONTROL_PADCONF_GPIO114, (IEN | PTD | EN | M7)) \
32 MUX_VAL(CONTROL_PADCONF_GPIO115, (IEN | PTD | EN | M7)) \
33 MUX_VAL(CONTROL_PADCONF_GPIO126, (IEN | PTD | EN | M7)) \
34 MUX_VAL(CONTROL_PADCONF_GPIO127, (IEN | PTD | EN | M7)) \
35 MUX_VAL(CONTROL_PADCONF_GPIO128, (IEN | PTD | EN | M7)) \
36 MUX_VAL(CONTROL_PADCONF_GPIO129, (IEN | PTD | EN | M7)) \
39 MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | DIS | SB_HIZ | M7)) \
42 MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PTD | EN | M7)) \
[all …]
/rk3399_rockchip-uboot/board/lg/sniper/
H A Dsniper.h79 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTD | DIS | M7)) \
87 MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M7)) /* safe_mode */ \
88 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M7)) \
89 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M7)) \
90 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M7)) \
99 MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)) /* safe_mode */ \
100 MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)) /* safe_mode */ \
101 MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)) /* safe_mode */ \
102 MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)) /* safe_mode */ \
109 MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)) /* safe_mode */ \
[all …]
/rk3399_rockchip-uboot/board/ti/am3517crane/
H A Dam3517crane.h83 MUX_VAL(CP(GPMC_A1), (M7))\
88 MUX_VAL(CP(GPMC_A6), (M7))\
91 MUX_VAL(CP(GPMC_A9), (M7))\
92 MUX_VAL(CP(GPMC_A10), (M7))\
111 MUX_VAL(CP(GPMC_NCS2), (M7))\
112 MUX_VAL(CP(GPMC_NCS3), (M7))\
113 MUX_VAL(CP(GPMC_NCS4), (M7))\
114 MUX_VAL(CP(GPMC_NCS5), (M7))\
115 MUX_VAL(CP(GPMC_NCS6), (M7))\
116 MUX_VAL(CP(GPMC_NCS7), (M7))\
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap5/
H A Dmux_omap5.h47 #define M7 7 macro
49 #define SAFE_MODE M7
H A Dmux_dra7xx.h51 #define M7 7 macro
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap4/
H A Dmux_omap4.h55 #define M7 7 macro
57 #define SAFE_MODE M7
/rk3399_rockchip-uboot/board/logicpd/zoom1/
H A Dzoom1.h105 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | DIS | M7)) /*GPMC_nCS2*/\
109 MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /*GPMC_nCS6*/\
/rk3399_rockchip-uboot/board/gumstix/duovero/
H A Dduovero_mux_data.h187 {PAD0_FREF_CLK0_OUT, (M7)}, /* safe mode */
188 {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */
/rk3399_rockchip-uboot/board/ti/beagle/
H A Dbeagle.h387 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
388 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
389 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
390 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
391 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
392 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap3/
H A Dmux.h49 #define M7 7 macro
/rk3399_rockchip-uboot/board/compulab/cm_t3517/
H A Dmux.c55 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); in set_muxconf_regs()
/rk3399_rockchip-uboot/board/compulab/cm_t35/
H A Dcm_t35.c166 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ in cm_t3x_set_common_muxconf()
/rk3399_rockchip-uboot/board/timll/devkit8000/
H A Ddevkit8000.h358 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
/rk3399_rockchip-uboot/board/ti/evm/
H A Devm.h393 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/\
/rk3399_rockchip-uboot/board/corscience/tricorder/
H A Dtricorder.h357 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
/rk3399_rockchip-uboot/board/ti/am57xx/
H A Dmux_data.h608 {XREF_CLK3, (M7 | PIN_INPUT)}, /* xref_clk3.hdq0 */